Part Number: TMS320F28388D
Hello, Experts,
I want to load and run specific user functions on SDRAM over EMIF.
So I've been testing my codes with reference to the example, emif_ex2_16bit_asram_codemem.c, in C2000.
Accessing 16 bit SDRAM as a storage like reading and writing a certain array on SDRAM is working well.
But when trying to access SDRAM as code memory, it got to be in fault generating the below error.
Some configuration and user codes to interface Async/Sync memory are like below.
- User defined functions
#pragma CODE_SECTION(add,".sdramfunc");
#pragma CODE_SECTION(multiply,".sdramfunc");
//
// Add - This function is for reference only. It will be copied to ASRAM
// and is executed from ASRAM.
//
uint16_t add(uint16_t a, uint16_t b)
{
return(a+b);
}
//
// Multiply - This function is for reference only. It will be copied to ASRAM
// and is executed from ASRAM.
//
uint16_t multiply(uint16_t a, uint16_t b)
{
return(a*b);
}
- async/sync configuration
void setupSdramParameter(void)
{
EMIF_SyncTimingParams tParam;
EMIF_SyncConfig conf;
//
// Configure SDRAM control registers
//
// Need to be programmed based on SDRAM Data-Sheet.
//T_RFC = 60ns = 0x6
//T_RP = 18ns = 0x1
//T_RCD = 18ns = 0x1
//T_WR = 1CLK + 6 ns = 0x1
//T_RAS = 42ns = 0x4
//T_RC = 60ns = 0x6
//T_RRD = 12ns = 0x1
//
//Emif1Regs.SDRAM_TR.all = 0x31114610;
tParam.tRfc = 6;
tParam.tRp = 1;
tParam.tRcd = 1;
tParam.tWr = 1;
tParam.tRas = 4;
tParam.tRc = 6;
tParam.tRrd = 1;
EMIF_setSyncTimingParams(EMIF1_BASE, &tParam);
//
//Txsr = 70ns = 0x7
//
//Emif1Regs.SDR_EXT_TMNG.all = 0x7;
EMIF_setSyncSelfRefreshExitTmng(EMIF1_BASE, 7);
//
//Tref = 64ms for 8192 ROW, RR = 64000*100(Tfrq)/8192 = 781.25 (0x30E)
//
//Emif1Regs.SDRAM_RCR.all = 0x30E;
EMIF_setSyncRefreshRate(EMIF1_BASE, 0x30E);
//
//PAGESIZE=1 (512 elements per ROW), IBANK = 2 (4 BANK), CL = 2,
//NM = 1 (16bit)
//
//Emif1Regs.SDRAM_CR.all = 0x00015521;
conf.pageSize = EMIF_SYNC_COLUMN_WIDTH_9;
conf.iBank = EMIF_SYNC_BANK_4;
conf.casLatency = EMIF_SYNC_CAS_LAT_2;
conf.narrowMode = EMIF_SYNC_NARROW_MODE_TRUE;
EMIF_setSyncMemoryConfig(EMIF1_BASE, &conf);
}
void EMIF_init(void)
{
EMIF_AsyncTimingParams tparam;
//
// Configure to run EMIF1 on full Rate. (EMIF1CLK = CPU1SYSCLK)
//
SysCtl_setEMIF1ClockDivider(SYSCTL_EMIF1CLK_DIV_2);
//
// Grab EMIF1 For CPU1.
//
EMIF_selectMaster(EMIF1CONFIG_BASE, EMIF_MASTER_CPU1_G);
//
// Disable Access Protection. (CPU_FETCH/CPU_WR/DMA_WR)
//
EMIF_setAccessProtection(EMIF1CONFIG_BASE, 0x0);
//
// Commit the configuration related to protection. Till this bit remains
// set, contents of EMIF1ACCPROT0 register can't be changed.
//
EMIF_commitAccessConfig(EMIF1CONFIG_BASE);
//
// Lock the configuration so that EMIF1COMMIT register can't be changed
// any more.
//
EMIF_lockAccessConfig(EMIF1CONFIG_BASE);
//
// Configure GPIO pins for EMIF1.
//
setupEMIF1PinmuxAsync16Bit(g_nMcuIndex);
//
// Configure for SDARM
//
setupSdramParameter();
//
// Configures Normal Asynchronous Mode of Operation.
//
EMIF_setAsyncMode(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_NORMAL_MODE);
//
// Disables Extended Wait Mode.
//
EMIF_disableAsyncExtendedWait(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET);
//
// Configure EMIF1 Data Bus Width.
//
EMIF_setAsyncDataBusWidth(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET,
EMIF_ASYNC_DATA_WIDTH_16);
//
// Configure the access timing for CS2 space.
//
tparam.rSetup = 2;
tparam.rStrobe = 5;
tparam.rHold = 2;
tparam.turnArnd = 0;
tparam.wSetup = 2;
tparam.wStrobe = 5;
tparam.wHold = 2;
EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tparam);
}
- link command
MEMORY
{
HWBIST : origin = 0x000000, length = 0x000020
/* BEGIN is used for the "boot to Flash" bootloader mode */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
RAMD0 : origin = 0x00C000, length = 0x000800
RAMD1 : origin = 0x00C800, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6TO7 : origin = 0x00B000, length = 0x001000
RAMGS0 : origin = 0x00D000, length = 0x001000
RAMGS1TO15 : origin = 0x00E000, length = 0x00F000
BEGIN : origin = 0x088000, length = 0x000002
VERSION : origin = 0x088008, length = 0x000008
FLASH4TO6 : origin = 0x088010, length = 0x017FF0
FLASH7TO10 : origin = 0x0A0000, length = 0x01A000
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
EMIF1_CS0n : origin = 0x80000000, length = 0x10000000
EMIF1_CS2n : origin = 0x00100000, length = 0x00100000
EMIF1_CS0_CS2n : origin = 0x00200000, length = 0x00100000
EMIF1_CS3n : origin = 0x00300000, length = 0x00080000
EMIF1_CS4n : origin = 0x00380000, length = 0x00060000
EMIF2_CS0n : origin = 0x90000000, length = 0x10000000
EMIF2_CS2n : origin = 0x00002000, length = 0x00001000
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
.text : > FLASH4TO6, ALIGN(8)
.cinit : > FLASH4TO6, ALIGN(8)
.switch : > FLASH4TO6, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMGS0
#if defined(__TI_EABI__)
.init_array : > FLASH4TO6, ALIGN(8)
.bss : >> RAMGS1TO15
.bss:output : > RAMLS4
.bss:cio : > RAMLS5
.data : > RAMLS5
.sysmem : > RAMLS5
/* Initalized sections go in Flash */
.const : >> FLASH4TO6, ALIGN(8)
#else
.pinit : > FLASH8, ALIGN(8)
.ebss : > RAMLS5 | RAMLS6TO7
.esysmem : > RAMLS5 | RAMLS6TO7
.cio : > RAMLS5 | RAMLS6TO7
/* Initalized sections go in Flash */
.econst : >> FLASH4 | FLASH5, ALIGN(8)
#endif
ramgs0 : > RAMGS0, type=NOINIT
//ramgs1 : > RAMGS1, type=NOINIT
ramm0 : > RAMM0, type=NOINIT
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT
MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT
MSGRAM_CLA_TO_CPU : > CLATOCPURAM, type=NOINIT
MSGRAM_CPU_TO_CLA : > CPUTOCLARAM, type=NOINIT
MSGRAM_CLA_TO_DMA : > CLATODMARAM, type=NOINIT
MSGRAM_DMA_TO_CLA : > DMATOCLARAM, type=NOINIT
#if defined(__TI_EABI__)
.sdramfunc : LOAD = FLASH4TO6,
RUN = EMIF1_CS0_CS2n,
LOAD_START(XintffuncsLoadStart),
LOAD_END(XintffuncsLoadEnd),
RUN_START(XintffuncsRunStart)
#else
.sdramfunc : LOAD = FLASH4TO6,
RUN = EMIF1_CS0_CS2n,
LOAD_START(_XintffuncsLoadStart),
LOAD_END(_XintffuncsLoadEnd),
RUN_START(_XintffuncsRunStart)
#endif
emif_cs0_nonfar : > EMIF1_CS0_CS2n
.farbss : > EMIF1_CS0n
.farconst : > EMIF1_CS0n
.em1_cs0 : > EMIF1_CS0n
.em1_cs2 : > EMIF1_CS2n | EMIF1_CS0_CS2n
.em1_cs3 : > EMIF1_CS3n
.em1_cs4 : > EMIF1_CS4n
.em2_cs0 : > EMIF2_CS0n
.em2_cs2 : > EMIF2_CS2n
}
Please check out whether there is anyting wrong.
If you have experiences as to this issue, I would like you to give some advice about a proper way using SRAM as program memory.
