Dear TI engineers,
I have a doubt in my work about spi between 28337s and 280230 or 280270.
Normally, communication of spi work well like pic1 below.
But, it could also not work like pic2 blow.
When fault happened, the SPIFFTX.BIT.TXFFST would be 4 which is the max value. So, data could not transmit. If fault have not happened, the SPIFFTX.BIT.TXFFST would be change from 0 to 4 in loop and data could send successfully.
So, do you have some idea?
Waiting for yours, best wishes,
coke.
Hi,
Gus, thanks for your reply.
Status of the bits shown below at pic1 in SPIFFTX are same in right and wrong state. Difference between them is whether bit of TXFFST could be changed to 0.
Configuration of spi was shown below in pic2.
Waiting for yours, best wishes,
coke.
Hi,
Gus, glad to hear your reply.
Configuration of GPIO have been shown in pic1. I have not thought this is the core of fault.
The four wires of spi in 28377s and 280230 is connect by 0 ohm resistance in the same board and have short distance. Certainly, GPIO of spi have been pulled up by 3.3v.
The only other thing I can think of is that the SPI is not receiving SPI_CLK signal.
What did you mean for this idea? From the pic above, SPI_CLK signal have successfully sent by 28377s. But it could not confirm whether this signal have been received by 280230？
Waiting for yours, best wishes,
coke.
Hi,
Gus, the picture below shown the GPIO CTRL registers in expressions window. It seemed like no problem.
The picture below shown the code.
Waiting for yours, best wishes,
coke
