TMS320F280025C: I2C interrupt ARDYINT, AASINT clarification and TX FIFO question

Chun-Lin Chen

Part Number: TMS320F280025C
Other Parts Discussed in Thread: C2000WARE

Dear TI expert,

I have alittle confuse about I2C interrupt and TX FIFO.

At TRM section 23.4.1 said, I2C general interrupt has 7 different source all ORed together.

I2C Interrupt Request	Interrupt Source
XRDYINT	Transmit ready condition: The data transmit register (I2CDXR) is ready to accept new data because the previous data has been copied from I2CDXR to the transmit shift register (I2CXSR). As an alternative to using XRDYINT, the CPU can poll the XRDY bit of the status register, I2CSTR. XRDYINT should not be used when in FIFO mode. Use the FIFO interrupts instead.
RRDYINT	Receive ready condition: The data receive register (I2CDRR) is ready to be read because data has been copied from the receive shift register (I2CRSR) to I2CDRR. As an alternative to using RRDYINT, the CPU can poll the RRDY bit of I2CSTR. RRDYINT should not be used when in FIFO mode. Use the FIFO interrupts instead.
ARDYINT	Register-access ready condition: The I2C module registers are ready to be accessed because the previously programmed address, data, and command values have been used. The specific events that generate ARDYINT are the same events that set the ARDY bit of I2CSTR. As an alternative to using ARDYINT, the CPU can poll the ARDY bit.
NACKINT	No-acknowledgment condition: The I2C module is configured as a master-transmitter and did not received acknowledgment from the slave-receiver. As an alternative to using NACKINT, the CPU can poll the NACK bit of I2CSTR
ARBLINT	Arbitration-lost condition: The I2C module has lost an arbitration contest with another master-transmitter. As an alternative to using ARBLINT, the CPU can poll the ARBL bit of I2CSTR.
SCDINT	Stop condition detected: A STOP condition was detected on the I2C bus. As an alternative to using SCDINT, the CPU can poll the SCD bit of the status register, I2CSTR.
AASINT	Addressed as slave condition: The I2C has been addressed as a slave device by another master on the I2C bus. As an alternative to using AASINT, the CPU can poll the AAS bit of the status register, I2CSTR.

I want more detail about ARDYINT and AASINT here.

First is Register-access ready condition (ARDYINT)

Assume using I2C under master transmit mode, is register-access ready condition happened when all data, which include start condition, address+read/write bit, data, and stop condition, all transmitted, so I can modify the I2C register safely? Or just simple mean all the I2C register (I2CSTR, I2CCNT ..etc.) can be access, but not mean all data had transfered?

I'm wondering this because I'm reviewing the library file "12cLib_FIFO_master_interrupt.c" in "I2c_ex6_eeprom_interrupt.c" Line 275

part of them is as below, I want to clearify the ueage of this interrupt to change master from transmitter mode into received mode.

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        case I2C_INTSRC_REG_ACCESS_RDY:
            I2C_disableInterrupt(base, I2C_INT_REG_ACCESS_RDY);
            I2C_disableInterrupt(base, I2C_INT_TXFF);
            I2C_disableFIFO(base);
            I2C_enableFIFO(base);
            I2C_setConfig(base, (I2C_MASTER_RECEIVE_MODE));
            I2C_clearInterruptStatus(base, I2C_INT_TXFF);
            if(I2C_Params->numofSixteenByte)
            {
                I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
            }
            else
            {
                I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)I2C_Params->remainingBytes);
            }
            I2C_setDataCount(base, I2C_Params->NumOfDataBytes);
            I2C_sendStartCondition(base);
            I2C_sendStopCondition(base);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

        case I2C_INTSRC_REG_ACCESS_RDY:
            I2C_disableInterrupt(base, I2C_INT_REG_ACCESS_RDY);
            I2C_disableInterrupt(base, I2C_INT_TXFF);
            I2C_disableFIFO(base);
            I2C_enableFIFO(base);
            I2C_setConfig(base, (I2C_MASTER_RECEIVE_MODE));
            I2C_clearInterruptStatus(base, I2C_INT_TXFF);
            if(I2C_Params->numofSixteenByte)
            {
                I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, I2C_FIFO_RXFULL);
            }
            else
            {
                I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)I2C_Params->remainingBytes);
            }

            I2C_setDataCount(base, I2C_Params->NumOfDataBytes);

            I2C_sendStartCondition(base);
            I2C_sendStopCondition(base);

            break;

Another is about Addressed as slave condition (AASINT)

Is this interrupt be generate only when I2C under slave mode or even it is master mode?

Is this interrupt can detect the ACK from specific address of slave?

In the same file above, the code change the role from slave transmitter to slave receiver (or vice versa?)

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        case I2C_INTSRC_ADDR_SLAVE:
            //Set TX / RX FIFO Level
            I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)(I2C_Params->NumOfAddrBytes));
            if((I2C_getStatus(base) & I2C_STS_SLAVE_DIR))
            {
                //Slave Transmitter (SDIR = 1)
                I2C_setConfig(base, I2C_SLAVE_SEND_MODE);
                //Enable TX FIFO interrupt and disable RXFF interrupt
                I2C_enableInterrupt(base, I2C_INT_TXFF);
                I2C_disableInterrupt(base, I2C_INT_RXFF);
                I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));
            }
            else
            {
                //Slave Receiver (SDIR = 0)
                I2C_setConfig(base, I2C_SLAVE_RECEIVE_MODE);
                //Fill dummy data in Transmit FIFO to clear pending FIFO interrupt flag
                //I2C_putData(base, 0xAA);
                //I2C_putData(base, 0x55);
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

        case I2C_INTSRC_ADDR_SLAVE:
            //Set TX / RX FIFO Level
            I2C_setFIFOInterruptLevel(base, I2C_FIFO_TXEMPTY, (I2C_RxFIFOLevel)(I2C_Params->NumOfAddrBytes));

            if((I2C_getStatus(base) & I2C_STS_SLAVE_DIR))
            {
                //Slave Transmitter (SDIR = 1)
                I2C_setConfig(base, I2C_SLAVE_SEND_MODE);
                //Enable TX FIFO interrupt and disable RXFF interrupt
                I2C_enableInterrupt(base, I2C_INT_TXFF);
                I2C_disableInterrupt(base, I2C_INT_RXFF);
                I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));
            }
            else
            {
                //Slave Receiver (SDIR = 0)
                I2C_setConfig(base, I2C_SLAVE_RECEIVE_MODE);
                //Fill dummy data in Transmit FIFO to clear pending FIFO interrupt flag
                //I2C_putData(base, 0xAA);
                //I2C_putData(base, 0x55);

                //Enable RX FIFO interrupt and disable TXFF interrupt
                I2C_disableInterrupt(base, I2C_INT_TXFF);
                I2C_enableInterrupt(base, I2C_INT_RXFF);
                I2C_clearInterruptStatus(base, (I2C_INT_TXFF|I2C_INT_RXFF));

            }
            break;

Additional question is about the mechanism of I2C FIFO transmission:

Assuming I2C in master transmit mode, and using i2c library provided by C2000Ware 4.02.00 \ driverlib \ i2c.c

I want to put data into I2C TX FIFO using I2C_putData(), and set FIFO level to 3, and also data counter I2CCNT = 3.

Before I2C_sendStartCondition(base) being operated, the data should keep inside the FIFO, or it will shiftout when I put the data into the TX buffer?

Is this mechanism same as I2C_sendStopCondition(base) ?

If I operate I2C_sendStartCondition(base) and immediately do I2C_sendStopCondition(base),

the I2C module will transmit: start condition, address+read/write bit, data, data, data, stop condition, is that right?

Though I still have question about I2C role change, but I think that is another topic.

Thanks for your help and hope my question can help others.

over 2 years ago

+1 Manoj Santha Mohan over 2 years ago

TI__Guru 55700 points

Chun-Lin Chen said:
Assume using I2C under master transmit mode, is register-access ready condition happened when all data, which include start condition, address+read/write bit, data, and stop condition, all transmitted, so I can modify the I2C register safely? Or just simple mean all the I2C register (I2CSTR, I2CCNT ..etc.) can be access, but not mean all data had transfered?

ARDY indicates that the I2C module registers are ready to be accessed because the previously programmed address, data, and command values have been used.

STOP condition doesn't need to be generated. ARDY is set at the end of each byte transmitted from I2CDXR.

Chun-Lin Chen said:
Another is about Addressed as slave condition (AASINT)

Is this interrupt be generate only when I2C under slave mode or even it is master mode?

I2C generates I2C Addressed As Slave (AAS) interrupt only when address mentioned in I2COAR is transmitted from another host. It doesn't matter whether I2C itself is configured as master.

Chun-Lin Chen said:
I want to put data into I2C TX FIFO using I2C_putData(), and set FIFO level to 3, and also data counter I2CCNT = 3.

Before I2C_sendStartCondition(base) being operated, the data should keep inside the FIFO

Yes, you need to use I2C_putData() to fill the TX FIFO before using I2C_sendStartCondition().

Chun-Lin Chen said:
the I2C module will transmit: start condition, address+read/write bit, data, data, data, stop condition, is that right?

When operating in non-repeat mode, you don't need to execute I2C_sendStopCondition(base) after all data is transmitted. It can done even in the beginning while START condition got generated.

When operating in repeat mode, you need to execute I2C_sendStopCondition(base) only after all data is transmitted.

Regards,

Manoj

0 Chun-Lin Chen over 2 years ago in reply to Manoj Santha Mohan

Prodigy 207 points

Thank you for the detail reply.

I can understand the master change the role due to the AARDY interrupt, also the slave recognise when master calling it is due to AAS interrupt.

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TMS320F280025C: I2C interrupt ARDYINT, AASINT clarification and TX FIFO question