TMS320F280049C: Does CPUTIMER1 interrupt automatically support nesting by Peripheral Interrupt?

Arief Rahman

Part Number: TMS320F280049C

Hi There TI Mastermind

My application currently use 4 interrupts:

ADCA1
SCIA_RX
CANA0
Timer 0/1/2 (just one of them, not all three)

The idea in my system is, I have two converters (both MCU controlled, with controller inside ADCA1 interrupt) connected in cascaded manner.

CANA0 interrupt is used to communicate with external supervisory control

Between two MCU, UART will be used to update each other status.

The SCIA_RX interrupt is used to receive the data from other MCU, and CPU TIMER interrupt is used to send the data to other MCU at a fixed time interval.

At the moment, both SCIA_RX and CANA0 interrupts can be nested by ADCA1.

My question is: for the timer used to adjust the time interval to send the data to the other MCU, I want this timer to be nested with the ADCA1.

The thing is, TIMER0 is located at the same PIE group with ADCA1, thus it will also interrupt CANA0 and SCIA_RX interrupts. And I dont want this to happen.

Lets say, you suggest to use TIMER1 or TIMER2 insteady, but is this TIMER1 or TIMER2 can be nested by SCIA_RX or CAN_RX interrupt?

Any suggestion?

I hope I make my question clear.

Thanks,
Arief

over 2 years ago

0 Vince over 2 years ago

TI__Mastermind 19795 points

Hi Arief,

Thanks for your question. I believe I understand your question. If I understand properly, all you need to do is nest and block certain interrupts from the same group, correct?

That is possible. Please see the following guide for details:

https://software-dl.ti.com/C2000/docs/c28x_interrupt_nesting/html/index.html

Please follow the above guide very carefully. There are a lot of things that can go wrong with SW nesting of interrupts, which the guide explicitly warns about. If you understand the guide above, then you can do what you have requested.

Regards,

Vince

0 Arief Rahman over 2 years ago in reply to Vince

Prodigy 10 points

Hi Vince

Yes I find those interrupt nesting guideline and has implemented it successfully.

So, now I have a different question:

1. That example is for peripheral interrupt. For TIMER1 and TIMER2, they are not routed through PIE system. Thus, there is no need to manually acknowledge the interrupt, right? so, is it enough to simply EINT; and DINT;? Can you please confirm if all of my ISR is correct as written below?

__interrupt void adcISR(void)
{
    GpioDataRegs.GPASET.bit.GPIO14 = 1;

    GpioDataRegs.GPACLEAR.bit.GPIO14 = 1;

    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
    // Acknowledge the interrupt
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

__interrupt void canaISR(void)
{
    uint32_t status;
    uint16_t aaa = 0;

    PieCtrlRegs.PIEACK.all = 0xFFFF;      // Enable PIE interrupts
    asm("       NOP");                    // Wait one cycle
    EINT;                                 // Clear INTM to enable interrupts

    #pragma MUST_ITERATE(10000, , 10000)
    for(aaa = 0; aaa<10001; aaa++)
    {}

    // Read the CAN-A interrupt status
    status = CanaRegs.CAN_INT.bit.INT0ID;

    CanaRegs.CAN_GLB_INT_CLR.bit.INT0_FLG_CLR = 1;

    DINT;
}

__interrupt void sciISR(void)
{
    PieCtrlRegs.PIEACK.all = 0xFFFF;      // Enable PIE interrupts
    asm("       NOP");                    // Wait one cycle
    EINT;                                 // Clear INTM to enable interrupts

    sci.rx_msg[0] = SciaRegs.SCIRXBUF.all;

    DINT;
}

__interrupt void timer1ISR(void)
{
    // GpioDataRegs.GPASET.bit.GPIO15 = 1;

    EINT;

    int i = 0;

    for(i = 0; i<1000; i++)
    {
        asm("       NOP");                    // Wait one cycle
    }

    DINT;

    // GpioDataRegs.GPACLEAR.bit.GPIO15 = 1;
}

2. Is there a way to ensure only adcISR can interrupt timer1ISR? I dont want the canaISR or sciISR interrupt the timer1ISR?

Thanks,
Arief,

0 Vince over 2 years ago in reply to Arief Rahman

TI__Mastermind 19795 points

Hi Arief,

These all look good assuming you are not wanting to re-arrange prioritization of any of the interrupts.

The problem is that for only allowing ADC to interrupt timer1, you NEED to do software prioritization. So you will need to follow the guide in the previous email to see how to ENABLE and DISABLE certain interrupts inside another interrupt.

Essentially, in any ISR that you want to change what can nest within it, you can manually choose which interrupts are allowed in that interrupt. So for the timer1ISR, you could ENABLE ONLY adcISR, and disable ALL OTHER ISRs.

Regards,

Vince

0 Arief Rahman over 2 years ago in reply to Vince

Prodigy 10 points

The group prioritization is accomplished by simply masking the IER by IER |= M_INT1 in the timer1ISR, canISR, and sciISR before setting the PIACK bit

Right?

Is there anything else I need to consider?

Thanks,
Arief,

+1 Vince over 2 years ago in reply to Arief Rahman

TI__Mastermind 19795 points

Hi Arief,

That's basically correct.

You only really need to modify the IER in the timer1ISR, and you would only enable IER for adcISR. The other interrupts, if you don't want anything nesting within them, you can leave alone. If you want to allow nesting in them too, then your statement in previous post is correct.

It only gets tricky (with more things to consider) if you start modifying the PIEIER bits within a group. Basically when you re-order interrupts within a group. Then there's a lot of extra precautions to take into account. But you are not re-ordering within groups, so it should be okay to just modify the IERs.

Regards,

Vince

0 Arief Rahman over 2 years ago in reply to Vince

Prodigy 10 points

Got it, really thanks,

It all worked well now...

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TMS320F280049C: Does CPUTIMER1 interrupt automatically support nesting by Peripheral Interrupt?