• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 83 subscribers
  • Views 414 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMDSCNCD28388D: TMDSCNCD28388D Design File Errors.

Vigneshwaran Marimuthu
Prodigy 10 points
Part Number: TMDSCNCD28388D


Hi Team,

This is Vigneshwaran from ABB India.

I am a senior layout designer in ABB.

We have recently bought TI Evaluation board("TMDSCNCD28388D") for our upcoming project.

We planned to take TI design file as reference and found quality related mistakes in design file. 

Link:MCU063B.GTL (ti.com)

I have verified both Layout and Gerber and listed findings below.(I know its out of my job, It will useful for next revision)

A) Dangling Vias : Signals routed on top layer but having vias. It will act as a stub.

B) No Proper Pinout or Routing

          

C) Diff Pair tuning missing

D)Silk on Pad

I request you to please have a look and correct in the next revision. I hope as its evaluation board, quality check not done before release it to Gerber.

Kindly ignore these are already corrected in the latest file.

Thanks and Regards,

Vigneshwaran.M

8088768710

  • 0
    TI__Mastermind 42195 points

    Vigneshwaran,

    I agree on the Via stubs.\

    Vigneshwaran Marimuthu said:

       

    This trace is actually quite hilarious. There was a lot of layout rework requested in this area, so I'm sure there was a trace originally blocking the obvious route, and it was apparently not caught in subsequent reviews.

    Vigneshwaran Marimuthu said:
     

    I actually don't take issue with the above traces. What is your suggestion here?

    Vigneshwaran Marimuthu said:
     

    Agree, avoiding this would be a best practice. If I remember correctly we typically set our acute angle rules a little lower than this so I don't believe this would get reported in DRC. (Anecdotally this trace hasn't caused any yield loss for this EVM)

    Vigneshwaran Marimuthu said:

    I agree that this isn't perfect and can be improved. Were talking very minor parasitic differences and an estimated <~10pS difference in delay, so in practice I don't believe this will have a significant impact. If you hold a difference of opinion, I'd be happy to hear it.

    Vigneshwaran Marimuthu said:

    I agree this one is pretty sad to have slipped by, but it has no bearing on the manufacturability.

    I actually appreciate the review. Without getting into the entire details the majority of these issues stem out of a few known issues at the time. This was actually a good time to review this previous experience from a younger version of myself. This gives me a good perspective for those I mentor.

    I've noted these changes along with the others existing for this design, but this board will very likely never get design recourses to revise.

    Regards,
    Cody