I am trying to create a CLA-ISR that is invoked by a EPWM interrupt, and it appears the CLA cannot write to ETCLR, so the CLA-ISR only gets called once. If I manually set ETCLR in the debugger, the CLA-ISR will be called one more time. I then added some code to CPU1 to also set ETCLR.bit.INT = 1, and the CLA-ISR gets called repeatedly.
The only thing I could find in the TRM is that CpuSysRegs.SECMSEL.bit.PF1SEL must be 0 for the CLA to have access to the peripheral-frame-1. I also have CPUSEL0 - 0, so EPWM8 belongs to CPU1 -- is there anything else that must be set to give the CLA1 write-access to EPWM8?
Also, in the debugger, I noticed something strange. The EPWM8.ETCLR register (from the TRM) is at address 0x47AA, so I added a __mdebugstop in the CLA and looked at the disassembly. The CLA1-ISR source is:
PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
EPwm8Regs.ETCLR.bit.INT = EPWM_CLEAR_INT_FLAG;
MEALLOW();
Cla1Regs.MICLR.bit.INT2 = 1;
MEDIS();
But the disassembly showed:
Shouldn't the MMOV32 instruction have address 0x47AA (EPWM8.ETCLR address from TRM) instead of 0x484C (which is somewhere in EPWM9)? I am using common header files between the CLA and CPU1 -- is this some problem with my CCS setup?
Thanks,
Jim
