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F28M35H52C: Shared RAM

Peter Berger
Prodigy 100 points
Part Number: F28M35H52C


Hi,

I can see in the data sheet two types of shared that seems to be accessible by both CPU's,

the first segment is written as "shared" but the second one is not,

both segments have address for the other CPU so i would assume all of the segments are shared, not only the one marked with the "shared" comment.

can you please elaborate what is the differences between memories marked shared and the ones that are not?

  • 0
    TI__Guru* 80640 points

    Peter,

    You are correct, in terms of what "Shared" is trying to communicate here both address spaces are shared between the 2 CPUs on the device.  Just a note that there is only one set of S0-S7 memories.  The table is showing that those are mapped to two different memory regions on each core; but the RAM is physically the same.  The big difference here is that the uDMA/DMA access is restricted to the 1st set of addresses.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 100 points

    Thanks,

    is it possible for me to use the memory in address range 2008 0000 – 2009 7FFF of RAM for my APP needs (see selected range in image)?

  • 0 in reply to Peter Berger
    TI__Guru 50611 points

    Peter,

    Matt is out of office on holiday break. Please expect response by first week of January. Sincere apology for inconvenience.

    Regards, Santosh

  • 0 in reply to Santosh Jha
    TI__Guru* 80640 points

    Peter, 

    This is fine, you just want to make sure that you don't use the corresponding alternate address(for code loading at least).  ex, there is only one C0 memory on the device, but it is mapped to 2 different address regions in each core.  

    As Santosh mentioned I'm "out", effective tomm through the year.  My response may be slow to nil during this time.

    Best,
    Matthew

  • 0 in reply to MatthewPate
    Prodigy 100 points

    Matthew,

    Thank you for the answer,

    The C0 address is mapped both to 2000 0000 – 2000 1FFF and 2008 0000 – 2008 1FFF, but effectively this is the same memory and i should configure it only once in the linker file.

    i guess the same is for memories C1 - C4.

    Question 1 : is it the same for all the Sx memories?

    e.g. is S0 memory can be configured twice in the linker for both address 2000 8000 – 2000 9FFF and 2008 8000 – 2008 9FFF and i can use both memory areas?

    if so, this would mean the master subsystem (M3 Core) has access to 128 KB of Sx memory + 32 KB of Cx memory, this is incorrect according to the datasheet specifying we have access to 64 + 32 KB of memory only.

    Question 2: if i can functionally use all of these memory areas only once, what would be the purpose of having two memory areas with same physical memory but different addresses?

    Sorry for the confusion and thank you for the assistance.

  • +1 in reply to Peter Berger
    TI__Guru* 80640 points

    Peter,

    Peter Berger said:
    The C0 address is mapped both to 2000 0000 – 2000 1FFF and 2008 0000 – 2008 1FFF, but effectively this is the same memory and i should configure it only once in the linker file.
    Peter Berger said:
    Question 1 : is it the same for all the Sx memories?

    This is correct, the is physically only one memory that exists for C0, even though it is mapped to two regions.  This is true for all memories that have the dual map, i.e. there is only one S0 RAM, etc.

    Peter Berger said:
    Question 2: if i can functionally use all of these memory areas only once, what would be the purpose of having two memory areas with same physical memory but different addresses?

    My understanding is that the dual mapping was done to accommodate the ARM Cortex M3 bit banding capability.

    Best,

    Matthew