TMS320F28379D:

Hi,

Can you share your PWM waveforms and CCS code to check it on my end. 

Best,

Uttam

Thank you for the reply,
here is the Code and the PWM waveforms that I get:
The code and the pictures are attached:

interrupt void adca1_isr(void)
{

V2pk=50;
del_theta=((0xFFFF)*Freq*500*(0.00000001));
theta=theta+del_theta;
V2_ref[2]=(int16_t)V2pk*(cos((float)theta*0.000095875)); //(2*pi)/65535=0.0000958751

if (theta==65535)
{
theta=0;
}

if (V2_ref[2]<0)
{
Vsec_ref[2]=-V2_ref[2];
}
else
Vsec_ref[2]=V2_ref[2];

//secondary dc link voltage sense
Vin[2] = (0.08319*(AdcaResultRegs.ADCRESULT2));
Vin[0]=(Vin[0]+Vin[1]+Vin[2])/3;
Vin[1]=Vin[2];
/* if (Vin[0]<41)
{
Vi[2] = Vin[0]- 0.1161*Vin[0]*Vin[0]+ 13.357*Vin[0] - 363.01;
}
else if (Vin[0]>41 && Vin[0]<80.4)
Vi[2] = Vin[0] - 8;
else if (Vin[0]>80.4 && Vin[0]<101)
Vi[2] = Vin[0]+ 0.4202*Vin[0] - 44.128;
else */
Vi[2] = Vin[0];
//
//voltage loop 1

V2dc_cnt_in[2] = Vsec_ref[2]-Vi[2]; //-Vi[2];
V2dc_cnt_out[2]=V2dc_cnt_out[1]+((KP_v2dc + Ki_v2dc*Ts/2)*V2dc_cnt_in[2]+(Ki_v2dc*Ts/2 - KP_v2dc)*V2dc_cnt_in[1]);
if(V2dc_cnt_out[2]>1.2) // 0.075
V2dc_cnt_out[2]=1.2;
if(V2dc_cnt_out[2]<-0.2) // 0.075
V2dc_cnt_out[2]=-0.2;
phi2=V2dc_cnt_out[2];
V2dc_cnt_in[1]=V2dc_cnt_in[2];
V2dc_cnt_out[1]=V2dc_cnt_out[2];
Vi[1]=Vi[2];
/*if(Vsec_ref[2]<100)
{
if (V2_ref[2]<0)
{
delta1=((1.57)*(1+a));
}
else
delta1=((1.57)*(1-a));

}
else
delta1=0;
if(delta1>1.5)
{
delta1=1.5;
}
else
delta1=delta1;
*/
if(Vsec_ref[2]<100)
{
delta1=((1.57)*(V2pk-Vsec_ref[2])/V2pk);
}

else
delta1=0;
if(delta1>1.5)
{
delta1=1.5;
}
else
delta1=delta1;
if(delta1<0)
{
delta1=0;
}
delta2=0;
delta3=0;
phi3=0;
ph2[2] = 159.155*(2*delta1);
ph3[2] = 159.155*(phi2+delta1-delta2);
ph4[2] = 159.155*(phi2+delta1+delta2);
ph5[2] = 159.155*(phi3+delta1-delta3);
ph6[2] = 159.155*(phi3+delta1+delta3);
/*
if (ph2>=250)
{
EPwm2Regs.CMPA.bit.CMPA=ph2+1;//ph2=249;
}
if (ph3>=250)
{
EPwm3Regs.CMPA.bit.CMPA=ph3+1;//ph3=249;
}
if (ph4>=250)
{
EPwm4Regs.CMPA.bit.CMPA=ph4+1;//ph4=249;
}
if (ph5>=250)
{
ph5=249;
}
if (ph6>=250)
{
ph6=249;
}
*/
//
if (250<ph2[1] && 250>ph2[2])
{
EPwm2Regs.CMPA.bit.CMPA=(ph2[2]+5);
}
else if (250>ph2[1] && 250<ph2[2])
{
EPwm2Regs.CMPA.bit.CMPA=(ph2[2]-5);
}
else
{
EPwm2Regs.CMPA.bit.CMPA=250;
}
if (250<ph3[1] && 250>ph3[2])
{
EPwm3Regs.CMPA.bit.CMPA=(ph3[2]-1);
}
else
{
EPwm3Regs.CMPA.bit.CMPA=250;
}
if (250<ph4[1] && 250>ph4[2])
{
EPwm4Regs.CMPA.bit.CMPA=(ph4[2]-1);
}
else
{
EPwm4Regs.CMPA.bit.CMPA=250;
}
if (250<ph5[1] && 250>ph5[2])
{
EPwm5Regs.CMPA.bit.CMPA=(ph5[2]-1);
}
else
{
EPwm5Regs.CMPA.bit.CMPA=250;
}
if (250<ph6[1] && 250>ph6[2])
{
EPwm6Regs.CMPA.bit.CMPA=(ph6[2]-1);
}
else
{
EPwm6Regs.CMPA.bit.CMPA=250;
}

if (ph2[2]>=0)
{
EPwm2Regs.TBPHS.bit.TBPHS = ph2[2];
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;
}
else if (ph2[2]<0)
{
EPwm2Regs.TBPHS.bit.TBPHS = -ph2[2];
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
}
//
if (ph3[2]>=0)
{
EPwm3Regs.TBPHS.bit.TBPHS = ph3[2];
EPwm3Regs.TBCTL.bit.PHSDIR = TB_DOWN;
}
else if (ph3[2]<0)
{
EPwm3Regs.TBPHS.bit.TBPHS = -ph3[2];
EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
}
//
if (ph4[2]>=0)
{
EPwm4Regs.TBPHS.bit.TBPHS = ph4[2];
EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN;
}
else if (ph4[2]<0)
{
EPwm4Regs.TBPHS.bit.TBPHS = -ph4[2];
EPwm4Regs.TBCTL.bit.PHSDIR = TB_UP;
}
//
if (ph5[2]>=0)
{
EPwm5Regs.TBPHS.bit.TBPHS = ph5[2];
EPwm5Regs.TBCTL.bit.PHSDIR = TB_DOWN;
}
else if (ph5[2]<0)
{
EPwm5Regs.TBPHS.bit.TBPHS = -ph5[2];
EPwm5Regs.TBCTL.bit.PHSDIR = TB_UP;
}
//
if (ph6[2]>=0)
{
EPwm6Regs.TBPHS.bit.TBPHS = ph6[2];
EPwm6Regs.TBCTL.bit.PHSDIR = TB_DOWN;
}
else if (ph6[2]<0)
{
EPwm6Regs.TBPHS.bit.TBPHS = -ph6[2];
EPwm6Regs.TBCTL.bit.PHSDIR = TB_UP;
}

ph2[1]=ph2[2];
ph3[1]=ph3[2];
ph4[1]=ph4[2];
ph5[1]=ph5[2];
ph6[1]=ph6[2];
//

AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}

void InitEPwm1Example()
{
EPwm1Regs.TBPRD = PERIOD; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0

EPwm1Regs.TBCTR = PERIOD;//0x0000; // Clear counter

//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

/* EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;*/

//
// Setup compare
EPwm1Regs.CMPA.bit.CMPA = PERIOD_HALF;
//PERIOD_HALF;

//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD= AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;

//
// Active Low PWMs - Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED.bit.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Disable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
EPwm1Regs.ETPS.bit.SOCAPRD = 2; // Generate pulse on 1st event
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
//
// Interrupt where we will change the Deadband
//
/*
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
*/
}

//
// InitEPwm2Example - Initialize EPWM2 configuration
//
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = PERIOD; // Set timer period
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTR = PERIOD;//0x0000; // Clear counter

// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
// EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow just to observe on
// the scope
// Setup compare
//EPwm2Regs.CMPA.bit.CMPA = PERIOD_HALF;

// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // Set PWM2A on Zero
EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR;

// Active Low complementary PWMs - setup the deadband
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED.bit.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED.bit.DBFED = EPWM2_MIN_DB;
EPwm2_DB_Direction = DB_UP;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
}

Hi Payam,

Code seems okay to me in terms of setting the ePWM. 

Can you commnet which ePWM module is missing the output? it might be due to logic error?

and if this is happening for one time, double check on the ISR logic.

Let me know if the problem still remains. 

Best,

Uttam

Thabk you Uttam,

ePWM2 is missing the cycle; the out is an AC waveform and at each AC period and at the same moment that is shown by the yellow waveform, the ePWM2 is missing.