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TMS320F28379S: Top side bypass capacitor design for nFBGA packages

John
Prodigy 230 points
Part Number: TMS320F28379S

Hello all,

We are designing a new system using "TMS320F28379SZWTT" devices, however, due to our design constraints like restrictions to mount the components only on one side plus the economics of the design, it's crucial for us to know if it's possible to put the bypass capacitances for the supply lines all around the BGA package on Top to avoid putting any components on the bottom? our goal will be to stick those capacitors almost to the borders of the package so they will have around the  7mm to - 8mm distance to the source.

By doing so, will the performance be affected negatively? if yes, on what aspects?

have you done such designs in TI and if there are any guides or considerations for us to take into account?

Regards
John

  • 0
    TI__Guru 50611 points

    Hi,

    The subject matter expert is out of office due to US holiday. Please expect response by 1st week of January. Sincere apology for inconvenience.

    Regards, Santosh

  • 0 in reply to Santosh Jha
    Prodigy 230 points

    Ok sure, I will await your feedback by then, thanks.

  • 0
    TI__Guru* 95315 points

    John,

             For decoupling caps, the general rule is to keep the trace length as short as possible. This is because we want to keep the trace (parasitic) inductance and the loop area as small as possible. You also want to keep layer changes to the bare minimum. I have reached out to some EMI experts for their input. Thank you for your patience.

  • 0 in reply to Hareesh Janakiraman
    Prodigy 230 points

    Thanks, Hareesh, 

    You are absolutely right, but due to design constraints, we highly prefer to keep the decouplings on the Top layers, the decouplings will be at the closest possible distance to VDDIO pins, around 5-8mm max almost stuck to the borders of the DSP package, we will also make sure the return ground path for these decouplings goes directly to the VSS pins of the DSP first by some star grounding technique, so very short discharge path for the returns too, butt in any case we need the capacitors to be on top.

    I understand this is not the best or recommended design, but making the boards two-sided has many negative impacts on our products, thus we want to avoid that.

    Thanks

    John

  • 0 in reply to John
    TI__Guru* 95315 points

    OK, I understand your requirements/constraints. Let us await to hear from other EMI experts. Many people are on vacation right now and will be back only in the first week of January.

  • +1 in reply to Hareesh Janakiraman
    TI__Guru* 95315 points

    John,

              I spoke to an EMI expert and following is the summary of our conversation: 

    If you look at our LauchPad, you can see that all decoupling caps are right below the IC on the bottom side. This offers the shortest trace length. The VDDIO/VDD pins connect to one end of the cap through a via and the other end of the cap connects to the GND plane through another via. In your proposed scheme, the trace length will increase since you are placing the caps along the periphery. The series inductance of the 5-8mm additional trace length cannot be neglected at frequencies of 200 MHz and its harmonics. In reality, the trace length is 2x (5 to 8mm) since the current has to close the loop and travel to the nearest GND point to the supply pin that is being decoupled.

    It is likely the effectiveness of the decoupling would be diminished in your scheme. Unfortunately, it is hard to quantify by how much.

    The important point to consider is if there is any emissions standard (like CISPR) that you are trying to meet. If not, you then have some leeway in your layout. If there is indeed a standard that your product must meet, you need to be careful. EMI issues are very costly to fix after the design is completed.

  • 0 in reply to Hareesh Janakiraman
    Prodigy 230 points

    Thanks, Hareesh for the suggestions, will take it into the account.

  • 0 in reply to John
    TI__Guru* 95315 points

    My colleague had this to say:

    "Having the caps 8mm away may affect radiated EMI and power integrity.

    At least keep a solid GND layer on layer 2 (directly under the IC) with < 6mils interlayer spacing. This maximizes the GND plane effectiveness and keeps the effective via path length as low as possible".

  • 0 in reply to Hareesh Janakiraman
    Prodigy 230 points

    Thanks, Hareesh, this is exactly what we were looking to do, so bringing a solid GND plane to the by-pass caps, separated from other returns, to making sure the path is minimized, thanks again for the guidance, we will test this and let you know if anything comes up.

    John.