This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: After adding a function in main(), project debug issue: C28xx_CPU2: Trouble Removing Breakpoint with the Action "Finish Auto Run" at 0x1bd27: (Error -1066 @ 0x1BD27)

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Hi champs,

I ask this for our customer.

Customer's CCS version is 10.2.0, compiler version is TI v20.2.5.LTS. Debugger tool is: Blackhawk xds200

Customer is currently running the code in C2000WARE (C2000Ware_3_04_00_00\device_support\f2837xd\examples\cpu1\cla_matrix_transpose), which can work normally when running directly. After the customer adds HILTestAsynchronousMotor_initialize() in main, the build can pass, but error message will appear in debug. The HILTestAsynchronousMotor_initialize() function is generated by MATLAB and added in the end of main(). The include path is added and build passed.

The Console window displays as follows:

C28xx_CPU1: GEL Output:

Memory Map Initialization Complete

C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.

C28xx_CPU1: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

C28xx_CPU2: GEL Output:

Memory Map Initialization Complete

C28xx_CPU2: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.

C28xx_CPU2: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

C28xx_CPU2: Trouble Removing Breakpoint with the Action "Finish Auto Run" at 0x1bd16: (Error -1066 @ 0x1BD16) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 9.3.0.00042)

About  "Finish Auto Run" error, Customer's Debugger Options setting is:

The HILTestAsynchronousMotor_initialize() function is:

void HILTestAsynchronousMotor_initialize(void)
{
  /* Registration code */

  /* states (dwork) */
  (void) memset((void *)&HILTestAsynchronousMotor_DW, 0,
                sizeof(DW_HILTestAsynchronousMotor_T));

  /* external inputs */
  (void)memset(&HILTestAsynchronousMotor_U, 0, sizeof
               (ExtU_HILTestAsynchronousMotor_T));

  /* external outputs */
  (void) memset((void *)&HILTestAsynchronousMotor_Y, 0,
                sizeof(ExtY_HILTestAsynchronousMotor_T));
}

And customer's project is only debug in CPU1 only, why CPU2 will report this issue?

Could you please help analyze why this error occurs after adding a function in main()? Thanks!

Best,

Julia

  • Hi Julia,

    Most of engineers are out of office due to US holiday, so responses will be delayed.

    In the function HILTestAsynchronousMotor_initialize() , what is the address HILTestAsynchronousMotor_DW, HILTestAsynchronousMotor_U, HILTestAsynchronousMotor_Y ?

    Regards, Santosh

  • Hi Santosh,

    Thanks for your reply! The struct variables are not addressed manually, they are global variables and allocated by compiler.

    Customer did more try here. When customer only add some part of code into the project, the CCS could jump to main after load. But if customer add more code into project, the CCS should no symbols loaded. They cannot add whole functions and only some part, If add one more line, the CCS cannot go main.

    So the question in my view is how to add large code into the demo project? Customer run this project in RAM and cmd file is:

    // The user must define CLA_C in the project linker settings if using the
    // CLA C compiler
    // Project Properties -> C2000 Linker -> Advanced Options -> Command File
    // Preprocessing -> --define
    #ifdef CLA_C
    // Define a size for the CLA scratchpad area that will be used
    // by the CLA compiler for local symbols and temps
    // Also force references to the special symbols that mark the
    // scratchpad are.
    CLA_SCRATCHPAD_SIZE = 0x100;
    --undef_sym=__cla_scratchpad_end
    --undef_sym=__cla_scratchpad_start
    #endif //CLA_C
    
    MEMORY
    {
    PAGE 0 :
       /* BEGIN is used for the "boot to SARAM" bootloader mode   */
    
       BEGIN               : origin = 0x000000,   length = 0x000002
       RAMM0           : origin = 0x000123,   length = 0x0002DD
       RAMD0           : origin = 0x00B000,   length = 0x000800
       RAMD1            : origin = 0x00B800,   length = 0x000800
       /* RAMLS4          : origin = 0x00A000, length = 0x000800 */
       /* RAMLS5           : origin = 0x00A800, length = 0x000800 */
       RAMLS4_5         : origin = 0x00A000,   length = 0x001000
       RESET               : origin = 0x3FFFC0,   length = 0x000002
    
    PAGE 1 :
    
       BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
       RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
    //   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
       RAMLS0          : origin = 0x008000,   length = 0x000800
       RAMLS1          : origin = 0x008800,   length = 0x000800
       RAMLS2                         : origin = 0x009000,   length = 0x000800
       RAMLS3                         : origin = 0x009800,   length = 0x000800
    
       RAMGS0           : origin = 0x00C000,   length = 0x001000
       RAMGS1           : origin = 0x00D000,   length = 0x001000
       RAMGS2           : origin = 0x00E000,   length = 0x001000
       RAMGS3           : origin = 0x00F000,   length = 0x001000
       RAMGS4           : origin = 0x010000,   length = 0x001000
       RAMGS5           : origin = 0x011000,   length = 0x001000
       RAMGS6           : origin = 0x012000,   length = 0x001000
       RAMGS7           : origin = 0x013000,   length = 0x001000
       RAMGS8           : origin = 0x014000,   length = 0x001000
       RAMGS9           : origin = 0x015000,   length = 0x001000
       RAMGS10          : origin = 0x016000,   length = 0x001000
    
    //   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */
    
    //   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
         RAMGS11          : origin = 0x017000, length = 0x006000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    //   RAMGS12          : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    //   RAMGS13          : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    //   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    //   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
    //   RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
                                                                /* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
       EMIF1_CS0n       : origin = 0x80000000, length = 0x10000000
       EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000
       EMIF1_CS3n       : origin = 0x00300000, length = 0x00080000
       EMIF1_CS4n       : origin = 0x00380000, length = 0x00060000
       EMIF2_CS0n       : origin = 0x90000000, length = 0x10000000
       EMIF2_CS2n       : origin = 0x00002000, length = 0x00001000
    
       CANA_MSG_RAM     : origin = 0x049000,   length = 0x000800
       CANB_MSG_RAM     : origin = 0x04B000,   length = 0x000800
    
       CLA1_MSGRAMLOW   : origin = 0x001480,   length = 0x000080
       CLA1_MSGRAMHIGH  : origin = 0x001500,   length = 0x000080
    }
    
    SECTIONS
    {
       codestart        : > BEGIN,      PAGE = 0
       .cinit           : > RAMM0,      PAGE = 0
       .switch          : > RAMM0,      PAGE = 0
       .reset           : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
    //   .stack           : > RAMM1,      PAGE = 1
       .stack           : > RAMM1,      PAGE = 1
       .text            : > RAMGS9|RAMGS10|RAMGS11,    PAGE = 1
    
    #if defined(__TI_EABI__)
       .bss             : > RAMLS2,    PAGE = 1
       .bss:output      : > RAMLS2,    PAGE = 1
       .init_array      : > RAMM0,     PAGE = 0
       .const           : > RAMLS3,    PAGE = 1
       .data            : > RAMLS3,    PAGE = 1
       .sysmem          : > RAMLS3,    PAGE = 1
    #else
       .pinit           : > RAMM0,     PAGE = 0
       .ebss            : > RAMLS2,    PAGE = 1
       .econst          : > RAMLS3,    PAGE = 1
       .esysmem         : > RAMLS3,    PAGE = 1
    #endif
       Filter_RegsFile  : > RAMGS0,        PAGE = 1
    
       .em1_cs0         : > EMIF1_CS0n, PAGE = 1
       .em1_cs2         : > EMIF1_CS2n, PAGE = 1
       .em1_cs3         : > EMIF1_CS3n, PAGE = 1
       .em1_cs4         : > EMIF1_CS4n, PAGE = 1
       .em2_cs0         : > EMIF2_CS0n, PAGE = 1
       .em2_cs2         : > EMIF2_CS2n, PAGE = 1
    
        /* CLA specific sections */
       Cla1Prog         : > RAMLS4_5, PAGE=0
    
       CLADataLS0                   : > RAMLS0, PAGE=1
       CLADataLS1                   : > RAMLS1, PAGE=1
    
       Cla1ToCpuMsgRAM  : > CLA1_MSGRAMLOW,   PAGE = 1
       CpuToCla1MsgRAM  : > CLA1_MSGRAMHIGH,  PAGE = 1
    
       /* The following section definition are for SDFM examples */
       Filter1_RegsFile : > RAMGS1,   PAGE = 1, fill=0x1111
       Filter2_RegsFile : > RAMGS2,   PAGE = 1, fill=0x2222
       Filter3_RegsFile : > RAMGS3,   PAGE = 1, fill=0x3333
       Filter4_RegsFile : > RAMGS4,   PAGE = 1, fill=0x4444
    
       ramgs0           : > RAMGS0,    PAGE = 1
       ramgs1           : > RAMGS1,    PAGE = 1
    
    #ifdef __TI_COMPILER_VERSION__
       #if __TI_COMPILER_VERSION__ >= 15009000
        .TI.ramfunc : {} > RAMM0,      PAGE = 0
       #else
        ramfuncs    : > RAMM0      PAGE = 0   
       #endif
    #endif
    
    #ifdef CLA_C
       /* CLA C compiler sections */
       //
       // Must be allocated to memory the CLA has write access to
       //
       CLAscratch       :
                         { *.obj(CLAscratch)
                         . += CLA_SCRATCHPAD_SIZE;
                         *.obj(CLAscratch_end) } >  RAMLS1,  PAGE = 1
    
       .scratchpad      : > RAMLS1,       PAGE = 1
       .bss_cla                              : > RAMLS1,       PAGE = 1
       .const_cla            : > RAMLS1,       PAGE = 1
    #endif //CLA_C
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    Sincerely appreciated and happy new year.

    Best,

    Julia

  • Julia,

    When the customer added the code, does it compile successfully? Does compiler/linker reports any error?

    Please ask the customer to review the mapfile.

    If they can send the project when it breaks, we can review it.

    Regards, Santosh 

  • Hi Santosh,

    When the customer added the code, does it compile successfully? Does compiler/linker reports any error?

     Yes, when customer click "build" it will be passed, no error is reported.

    Customer's map file is as follows:

    https://tidrive.itg.ti.com/a/autCrvDrQqR460Kx/1bec57c6-c4bc-4408-af49-4a1c12ee4b4d?l

    I will send the customer's project to you offline, thank you!

    Best,

    Julia

  • Julia,

    Looks like it may be stack overflow.

    Please try to increase the stack and then check it again.

    Regards, Santosh

  • Hi Santosh,

    Thanks for your reply! Could you provide more information and cues about the “stack overflow”? And how to set more space for stack in the C2000 project configuration?

    Thank you very much.

    Best,

    Julia

  • Hi Julia,

    Please refer to this link on how to detect the stack overflow.

    https://www.ti.com/lit/an/spra820/spra820.pdf

    Regards, Santosh