TMS320F28379D: Missing documentation on the CLB

Hi

Thanks for the answer,

While it did not really solve the issue, the completion of that backlog item probably will however, So i will mark it resolved.

As a really nice to have, Has this backlog item gotten a  Jira number, that I can follow to get update on the progress?

Also please fell free to send a draft for review, when you get there.

Suggestion: Add some comment to the documentation in C200Ware driverlib functions, about this.

Example 1

//*****************************************************************************
//
//! Set global enable.
//!
//! \param base is the base address of a CLB tile's logic config register.
//!
//! This function enables the CLB via global enable register.
//!
//! \note CLBx shares the clock with EPWMx. So to enmable CLB1, do enable EPWM1 clock.
//!
//! \return None.
//
//*****************************************************************************
static inline void CLB_enableCLB(uint32_t base)

Example 2

//*****************************************************************************
//
//! Enables a peripheral.
//!
//! \param peripheral is the peripheral to enable.
//!
//! Peripherals are enabled with this function.  At power-up, all peripherals
//! are disabled; they must be enabled in order to operate or respond to
//! register reads/writes.
//!
//! \note Note that there should be atleast 5 cycles delay between enabling the
//! peripheral clock and accessing the peripheral registers. The delay should be
//! added by the user if the peripheral is accessed immediately after this
//! function call.
//! Use asm(" RPT #5 || NOP"); to add 5 cycle delay post this function call.
//!
//! \note CLB and EPWM shares the same clock, to enable a CLB use the coresponding EPWM.
//!       so a call with SYSCTL_PERIPH_CLK_EPWM1 will also enable CLB1, SYSCTL_PERIPH_CLK_EPWM2 will also enable CLB2 and so forth.
//! \return None.
//
//*****************************************************************************
static inline void
SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral)

You might want to phrase it shorter, but just having the CLB and EPWM mentioned here, would raise awareness and make me seek more info.

It will not replace the need for a proper doc, but still way better than not knowing at all.

I think these notes should also appear in the Sysconfig tool, in the CLB chapters.

Have a followup question.

In the refenerence manual SPRUHM8I–December 2013–Revised September 2019

in figure 26-5 (p2786) is the outputs named CLBx_OUT0 to CLBx_OUT15, but in the table below they are named  to CLBx_OUT7_0 and then CLBx_OUT1_0 to CLBx_OUT1_7, I assume that they map so CLBx_OUT9 == CLBx_OUT1_1 ?

The CLB_OUT_EN register is a 32 bit register, and the text tells that each bit enables an output, but how does that map to the 16 outputs mentioned in chapter 26.3.

Looking in driverlib function CLB_setOutputMask, there is provided defines (CLB_OUTPUT_xx) for all 32 bits also?