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TMS320F28379D: XTAL Clock integrity check using TIMER2

Part Number: TMS320F28379D


Hello,

I read in few datasheet that TIMER2 could be used to measure the XTAL (external clock 20MHz) drift.

I would really like to implement this integrity check due to the criticality of this XTAL drift in our design.

I cannot find a lot of design reference or example on this topic.

Can someone explain to me how it works and how to configure it?

I imagine that I would use XTAL as a input clock for TIMER2 and that SYSCLK (PLL) would be the High frequency sampling clock.

But I don't know how it works internally and how to configure it. I would imagine that if XTAL drift then SYSCLK (PLL) would drift as well!

Thank you

  • I read in few datasheet that TIMER2 could be used to measure the XTAL (external clock 20MHz) drift.

    Can you please point me to the document/page number etc?

    It is indeed possible to measure the existence of a clock source by connecting it to CPU Timer 2 and checking if it is incrementing. Typically, this is done before switching to that clock source. Below from page 119 of www.ti.com/lit/SPRUHM8:

    CPU timers 0 and 1 are connected to PERx.SYSCLK. Timer 2 is connected to PERx.SYSCLK by default,
    but may also be connected to INTOSC1, INTOSC2, XTAL, or AUXPLLCLK via the TMR2CLKCTL register.
    This register also provides a separate prescale divider for timer 2. If a source other than SYSCLK is used,
    the SYSCLK frequency must be at least twice the source frequency to ensure correct sampling

  • The Document number is sprui78d - Functional Safety Manual for TMS320F2837xD.

    I need to point out that I am not trying to check the existence of the clock, I am trying to check if the main clock drift (XTAL or SYSPLL).

    The statement is the following on page 45:

    6.1 C2000 MCU Infrastructure Components
    6.1.1 Clock Integrity Check Using CPU Timer


    It is recommended to use the CPU Timer module to detect incorrect clock frequencies and drift between clock sources. CPU Timer2 has a programmable counter whose prescale value and clock source can be selected. Using the system clock as reference time base and frequency relationship between selected clock and system clock can be ascertained. For more information on the clock selection options implemented, see the device specific data sheet. Higher diagnostic coverage can be obtained by setting tighter bounds when checking clock integrity using Timer2. Common cause failures can be reduced by using different clock sources and different prescale values for the reference clock and measured clock. The Timer diagnostic is not enabled by default and must be enabled via software. The cyclical check applied by the Timer module provides an inherent level of self-checking (auto-coverage), which can be considered for application in latent fault diagnostics.

    Thank you

    Laurent

  • Laurent,

              I have reached out to the safety experts in the team. I will let you know what I find. Thank you for your patience.

  • Thank you, I appreciate it.

  • Laurent,

                  In the F2837x SDL, we implemented this by having the CPU Timer 2 configured to run based on a different clock source than SYSCLK. So, if SYSCLK is based on the XTAL, you can configure Timer 2 to use INTOSC2, and then use Timer 2 to measure some known interval—like a delay loop in software or the internal between 2 periodic interrupts—and check that the elapsed time is within an expected range. One thing to be cognizant of though is that the accuracy of the INTOSC itself is ±3%. In other words, INTOSC frequency itself would change over temperature. Since the magnitude and direction of shift would likely be different between the XTAL and INTOSC, the proposed method is still useful to determine shifts in frequency. 

    On a different note, the content in the Safety manual has a typo and hence doesn’t read well. The corrected sentence is below: 

    "Using the system clock as reference time base, the frequency relationship between selected clock and system clock can be ascertained".

  • Thank you Hareesh, that makes perfect sense.

    Laurent