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TMDSCNCD28388D: three issues about memory

Ben Qin
Intellectual 2690 points
Part Number: TMDSCNCD28388D


Hi Team,

There are three questions from the customer:

1.What difference between LS0RAM,M0RAM and D0RAM?

2.Can I put section such as .text,.bss,.stack and the other section into GSRAM? I'm not sure what the latency is.

3. I found usually program section and data section are kept separate in cmd file, is there have latency if I put program and data section in LSRAM?(I tested it with my lamp program and found it to work but not sure if it was a hidden problem)

Could you help check this case?

Thanks & Regards,

Ben

  • +1
    TI__Guru** 115881 points

    Hi,

    Ben Qin said:
    1.What difference between LS0RAM,M0RAM and D0RAM?

    All RAMs are 0 wait state on this device. We have provided different RAM names based on accessibility from different initiators or security feature or ECC/Parity

    LS0RAM are accessible from CPU as well as CLA where as M0 and D0 RAMs are accessible from CPU only. LS0 and D0 RAMs can be made secure where as M0 RAM is non-secure. These details can be find in device datasheet (Memory Map section).

    Ben Qin said:
    3. I found usually program section and data section are kept separate in cmd file, is there have latency if I put program and data section in LSRAM?(I tested it with my lamp program and found it to work but not sure if it was a hidden problem)

    If both data and code is mapped in same RAM block, there could be arbitration if data and program accesses are happening at same time (depends on program). If both are mapped into different RAM block then arbitration penalty will not be there.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Intellectual 2690 points

    Hi Vivek,

    Thanks for you reply.

    But I am not quite clear about two nouns that you mentioned. First what does ''secure'' mean('security' in the TRM)? Second what does "arbitration penalty" mean? Are there any related documents?

    Best Regards,

    Ben

  • 0 in reply to Ben Qin
    TI__Intellectual 2690 points

    Hi Vivek,

    May I know there are any updates?

    Best,

    Ben

  • 0 in reply to Ben Qin
    TI__Guru** 115881 points

    Hi Ben,

    Ben Qin said:
    First what does ''secure'' mean('security' in the TRM)?

    Yes, it is security.

    Ben Qin said:
    Second what does "arbitration penalty" mean? Are there any related documents?

    For the memories which can be accessed from multiple initiator and if both try to access at same time then arbitration will be done which means one of the access will be stalled and it'll only go through after other access is finished. You can get mode detail about it in section "3.12.1.7 Access Arbitration" of TRM.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Intellectual 2690 points

    Hi Vivek,

    Thanks for your reply.

    But I still have a little doubts with security, I want to know what is security do, for example, two types of MsgRAM, one have security, and the other have not.

    So what is the security do?

    Best,

    Ben

  • +1 in reply to Ben Qin
    TI__Guru** 115881 points

    Ben,

    Security logic blocks read/write access to secure memories by code running from non-secure region. So in this case the MSGRAM which is secure (its configurable by user so user can make it secure if needed) can be read or written by code running from secure memory only where as other MSGRAM (which is non-secure) can be read or written by code running from any memory.

    Regards,

    Vivek Singh