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TMS320F28377D: sigma-delta sampling synchronization configuration questions

Hui Chen
Intellectual 890 points

Part Number: TMS320F28377D

Hello there,

I would like to ask about the sigma-delta sampling module in chip F28377D. According to the specification, the condition of PWM11's CMPC synchronizing sdfm module is that one pwm cycle can only generate one CMPC event, what exactly does this event refer to? What would happen if there were two CMPC events. Whether the synchronization configuration of the CMPC of PWM11 to the sdfm module is the same as the event triggering configuration in ET, and whether it is affected by the synchronization configuration in ET.

Please let me know if you have any hint.

Thanks in advance.

Best regards

huichen

  • 0
    TI__Mastermind 30431 points
    Hui Chen said:
    According to the specification, the condition of PWM11's CMPC synchronizing sdfm module is that one pwm cycle can only generate one CMPC event, what exactly does this event refer to?

    It refers to the CMPC events generated from the Counter Compare modules in the PWM module.

    Hui Chen said:
    What would happen if there were two CMPC events.

    Per TRM, "Ensure that ONLY ONE SDSYNC event will be generated per PWM timer period. Using PWM in up-count or down-count mode would automatically ensure that you get ONLY SDSYNC event. But, if up-down count mode is used, then make sure that only one SDSYNC event per PWM cycle is generated; otherwise, the filter synchronizer will corrupt SDFM timing by providing two pulses per PWM cycle. "

    Hui Chen said:
    Whether the synchronization configuration of the CMPC of PWM11 to the sdfm module is the same as the event triggering configuration in ET, and whether it is affected by the synchronization configuration in ET.

    The ET module only generates EPWMxINT and EPWMxSOC signal, not the SDSYNC signal.