Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: C2000WARE
Hello,
SCIB randomly gets stuck in repeating SW resets inside the RX ISR. That seems to follow repeating 16 byte data bursts with 200ms blanking between 2 such data bursts. Oddly the OE register flag is never set or rapidly cleared by the SW reset but SCIprtinf() reports 0x4004, assuming OE flag. When RX FIFO data bursts are short (8 bytes) everything works as expected. The CPU seems to lag behind reading RX buffer, OE trips SW reset, not always the case.
TRM states SCIB TX FIFO is supposed to give RX FIFO priority, that seems to be part of the problem as it keeps transmitting data during RX burst events.
Q1: Why SW reset never exists the RX ISR via (return, clear ACK, DINT) statements being above the ISR__attribute__((interrupt)) C2000 compiler adds IRET inside eabi projects?
Also tried using _asm(" IRET") rather than (return) after SW reset and RX FIFO just dead locks. The only way to clear the SW reset loop requires MCU cold reset. I located file (DSP28_SWPrioritizedIsrLevels.h) deep dive C2000ware_4.01 driverlib, below link nesting rules page mentions. Links text is unclear if that file is part of an example project or mandated for correct peripheral core priority order regardless of tandem groups nesting.
It seems wrong to assume individual groups require nesting as the core priority order is supposed to control inner group core flags. The word Nesting in CPU instruction sets infers one routine exists inside the other, not working in tandem as depicted by TRM 3.3.5 table 3-3 and 3.5.6. A drill down tree illustration might better explain what TRM means by adding words (tandem Group nesting) not just saying one word (nesting) as peripheral core priority controls each inner group pending ISR's and PIE priority so no tandem group nesting should even be required. Yet that does not seem to work as the TRM has depicted the PIE IER group interrupt priority model. Suggesting the groups peripheral core priority silicon has some kind of errata and requires the file (DSP28_SWPrioritizedIsrLevels.h) to work correctly.
Q2: Does that file have to be part of the project for peripheral core priory PIEIER flags to correctly work?
https://processors.wiki.ti.com/index.php/Interrupt_Nesting_on_C28x
