[CONCERTO F28M35x] Technical Reference Manual on the web

Interesting to get further information on the chip :o) I am looking forward to take hands on the beast !

Are you going to keep the manual in that format or will you split documents like it's done on the TMS320 series ?

Regards,
Clément Letonnelier 

Clément,

Moving forward the documentation will be in one TRM (technical reference manual) instead of separate documents. 

Regards,

Lori

Lori Heustess said:

Moving forward the documentation will be in one TRM (technical reference manual) instead of separate documents.

Very big document and it is hard to navigate and scroll. Separate documents was good in c28xx though for the first time it was unusual after spru357 for c24xx.

When the chapters about EPWM will appear in this document? It's very important for me because I'm developing a new device and need an exact information about pins for hardware fault input from IGBT-drivers.

Thank you.

Here is the schedule we are trying to work with on the TRM updates

 (9/9):

1.       M3 uDMA

2.       ADC/Analog

3.       M3 UART

4.       M3 SSI

5.       M3 EPI

6.       System Control (includes IPC)

 (9/31):

1.       C28 ePWM

2.       C28 HRPWM 

3.       Internal Memory (Flash and RAM)

4.       Boot ROM

Very bad. I have to make PCB until the end of september and have no information about fate of "/TZn" pins to design fault inputs.

Anuchin,

On concerto a large chunk of the GPIO's (0-63) can be mapped as TZn pin's,

Is this TZn from an external circuit? or are you using the internal comparator trip to the PWM?

-Manish Bhardwaj

Nice - one thousand papers document! (be more...)

Very helpfull. Thanks.

Manish Bhardwaj said:

Anuchin,

On concerto a large chunk of the GPIO's (0-63) can be mapped as TZn pin's,

Is this TZn from an external circuit? or are you using the internal comparator trip to the PWM?

-Manish Bhardwaj

What does it mean "a large chunk"? If any of GPIO then its solves a problem, if some of them then I need exact list to design PCB.

Thank you

Manish Bhardwaj said:

Anuchin,

On concerto a large chunk of the GPIO's (0-63) can be mapped as TZn pin's,

Is this TZn from an external circuit? or are you using the internal comparator trip to the PWM?

-Manish Bhardwaj

Alecksey Anuchin said:

What does it mean "a large chunk"? If any of GPIO then its solves a problem, if some of them then I need exact list to design PCB.

Alecksey,

Any I/O: GPIO0 to GPIO63 can be defined as a trip input.

There is a configuration register for each trip input (i.e. GPTRIP1SEL, GPTRIP2SEL.... GPTRIP12SEL) . 

The software specifies which pin, GPIO0 to GPIO63, is connected to the particular trip input. 

i.e.

0000 = GPIO0
0001 = GPIO1.....111111 = GPIO63.

There is an example in controlSUITE (www.ti.com/controlsuite) that shows how you would configure GPIO16 and GPIO17 as TZ1n and TZ2n.

\ti\controlSUITE\device_support\F28M35x\vBeta1\F28M35x_examples_Control\epwm_trip_zone\

Regards,

Lori

The following chapters have been updated:

• M3 EPI
• M3 uDMA
• M3 SSI
• M3 UART
• Analog subsystem

Hi Lori,

   thanks for the update.  This was on-time as promised. Are you still on track to release the other chapters on 31/09/2011.  The boot code and programming strategy are important for standalone applications.  I have a controlcard board to evaluate with, but getting an understanding of how to get the 2 processors to communicate and operate together is the most important thing.  Are TI planning to release any example applications that have the M3 as the interface/host, and the C28x as the control device?

thanks,

Greg