TMS320F280025C: CAN receive frame configuration, transmit is ok (polling mode)

DAMIEN CHARNAY

Part Number: TMS320F280025C

Hi experts,

I need your help^for my program, I want to configure CAN communication I have for the moment for the development my board for the first node and my PC with a peak CAN probe for the second node.

I want to transmit one object and receive a second one for the moment but then I will have more to configure. The tranmission is good, I see my frame from the board to my PC but the opposit doesn't work in CAN_IF2DATA / CAN_IF2DATB I see never data.

I am trying to set up a filter on the incoming ID I only want to accept the ID I send from the PC in this case ID = 0x010 in standard form.

I have done a lot of research in your documentation and on the forum but without success. I tried to configure without the filter on the ID by not putting masks but without success, so I am not sure that the problem comes from the filtering on the ID (to see if I did not make a mistake anyway)

So I configure :

CanaRegs.CAN_IF2MSK.bit.Msk = 0x1FFFFFFF;

CanaRegs.CAN_IF2ARB.bit.ID = (msgID << 18);

CanaRegs.CAN_IF2CMD.bit.DIR = 0;

CanaRegs.CAN_IF2ARB.bit.Dir = 0;

This lines are correctly ? for me yes but ...

You can see screenshots and my code :

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void can_init(void)
{
    EALLOW;
    /// Configure CANA_RX
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;     /// Disable the pullup on GPIO3
    GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 3;    /// To define mux position, mux position equal GPAGMUX(2bits) - GPAMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2;    /// GPIO3 = CANA_RX, see pin attributes documentation for mux position.
    GpioCtrlRegs.GPADIR.bit.GPIO3 = 0;     /// GPIO3 = input
    GpioCtrlRegs.GPAINV.bit.GPIO3 = 0;   /// Not inverted GPIO input
    /// Configure CANA_TX
    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;     /// Disable the pullup on GPIO2
    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;     /// GPIO2 = output
    GpioCtrlRegs.GPAODR.bit.GPIO2 = 0;     /// Normal output not open drain
    GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0;   /// Synchronous
    GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 3;   /// To define mux position, mux position equal GPBGMUX(2bits) - GPBMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2;    /// GPIO2 = CANA_TX, see pin attributes documentation  for mux position.
    /// Place CAN controller in init state, regardless of previous state.
    /// This will put controller in idle, and allow the message object RAM to be programmed.
    /// CAN module ignore bus activity during configuration.
    CanaRegs.CAN_CTL.bit.Init = 1;
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void can_init(void)
{
    EALLOW;
    /// Configure CANA_RX
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;     /// Disable the pullup on GPIO3
    GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 3;    /// To define mux position, mux position equal GPAGMUX(2bits) - GPAMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2;    /// GPIO3 = CANA_RX, see pin attributes documentation for mux position.
    GpioCtrlRegs.GPADIR.bit.GPIO3 = 0;     /// GPIO3 = input
    GpioCtrlRegs.GPAINV.bit.GPIO3 = 0;   /// Not inverted GPIO input

    /// Configure CANA_TX
    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;     /// Disable the pullup on GPIO2
    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;     /// GPIO2 = output
    GpioCtrlRegs.GPAODR.bit.GPIO2 = 0;     /// Normal output not open drain
    GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0;   /// Synchronous
    GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 3;   /// To define mux position, mux position equal GPBGMUX(2bits) - GPBMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2;    /// GPIO2 = CANA_TX, see pin attributes documentation  for mux position.
    /// Place CAN controller in init state, regardless of previous state.
    /// This will put controller in idle, and allow the message object RAM to be programmed.
    /// CAN module ignore bus activity during configuration.
    CanaRegs.CAN_CTL.bit.Init = 1;
    /// CAN software reset.
    CanaRegs.CAN_CTL.bit.SWR = 1;
    /// The CPU has write access to the configuration register.
    CanaRegs.CAN_CTL.bit.CCE = 1;
    /// Clock and timing bit configuration
    ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0;
    /// Set up the bit rate for the CAN bus, with 250kbit/s.
    /// Bit time (Tq) = 8
    /// Bit clock prescaler = 49dec = 0x31
    /// Propagation segment (Tq) = 1
    /// Phase segment 1 (Tq) = 3dec = 0x3
    /// Phase segment 2 (Tq) = 2dec = 0x2
    /// Synchronization jump width (Tq) = 2dec = 0x2
    /// Sampling point = 62.5%
    /// Oscillator tolerance = 1.48%
    /// Set Baud rate prescaler.
    CanaRegs.CAN_BTR.bit.BRP = 0x31;
    /// Synchronization jump width.
    CanaRegs.CAN_BTR.bit.SJW = 0x2;
    /// Time segment before the sample point.
    CanaRegs.CAN_BTR.bit.TSEG1 = 0x3;
    /// Time segment after the sample point.
    CanaRegs.CAN_BTR.bit.TSEG2 = 0x2;

    /// CAN module processes messages normally
    CanaRegs.CAN_CTL.bit.Init = 0;

    //setupMessageObject(1, 0x100, MSG_OBJ_TYPE_TRANSMIT);
    setupMessageObject(2, 0x010, MSG_OBJ_TYPE_RECEIVE);
    EDIS;
}

...
    /// Receive message
    else
    {
        /// Wait for busy bit to clear.
        while(CanaRegs.CAN_IF2CMD.bit.Busy)
        {
        }
        /// Clear and Write out the registers to program the message object.
        CanaRegs.CAN_IF2CMD.all = 0;
        CanaRegs.CAN_IF2MSK.all = 0;
        CanaRegs.CAN_IF2ARB.all = 0;
        CanaRegs.CAN_IF2MCTL.all = 0;

        /// Use mask (Msk, MXtd and Mdir) for acceptance filtering.
        CanaRegs.CAN_IF2MCTL.bit.UMask = 1;
        /// Set the data length since this is set for all transfers. This is also a single transfer and not a FIFO transfer so set EOB bit.
        /// Data frame has 8 data bytes
        CanaRegs.CAN_IF2MCTL.bit.DLC = 9;
        /// The message object is a single message object or the last message object in a FIFO buffer.
        CanaRegs.CAN_IF2MCTL.bit.EoB = 1;
        /// Extended identifier bit has no effect on the acceptance filtering (standard mode is used).
        CanaRegs.CAN_IF2MSK.bit.MXtd = 0;
        /// The message direction bit has no effect on the acceptance filtering.
        CanaRegs.CAN_IF2MSK.bit.MDir = 0;
        /// The corresponding bit in the identifier of the message object is used for acceptance filtering.
        CanaRegs.CAN_IF2MSK.bit.Msk = 0x1FFFFFFF;

        /// IF command registers configure and initiate the transfer between the IF register sets and the message RAM.
        /// Set the Control, Mask, and Arb bit so that they get transferred to the message object.
        /// The message control bits will be transferred from the IF2 register set to the message object.
        CanaRegs.CAN_IF2CMD.bit.Control = 1;
        /// The arbitration bits will be transferred from the IF2 register set to the message object.
        CanaRegs.CAN_IF2CMD.bit.Arb = 1;
        /// The mask bits (Identifier mask + Mdir + MXtd) will be transferred from the IF2 register to the message object.
        CanaRegs.CAN_IF2CMD.bit.Mask = 1;
        /// Read message object (mail box).
        CanaRegs.CAN_IF2CMD.bit.DIR = 0;
        /// Transfer data to message object RAM
        CanaRegs.CAN_IF2CMD.bit.MSG_NUM = objID;

        /// Arbitration
        /// Transmit direction = receive, a remote frame with the identifier of this message object is transmitted.
        CanaRegs.CAN_IF2ARB.bit.Dir = 0;
        /// Set Message ID.
        CanaRegs.CAN_IF2ARB.bit.ID = (msgID << 18);
        /// Standard identifier is used for this message object.
        CanaRegs.CAN_IF2ARB.bit.Xtd = 0;
        /// Mail box is enabled after mask configuration.
        CanaRegs.CAN_IF2ARB.bit.MsgVal = 1;
    }
}

Read data function
bool receive_CAN_message()
{
    bool status;

    /// Detect for mail box number 2 (receive)
    //if(CanaRegs.CAN_NDAT_21 == 2)
    //{
        // Set the Message Data A, Data B to be read on request for data from the message object.
        CanaRegs.CAN_IF2CMD.bit.DATA_A = 1;
        CanaRegs.CAN_IF2CMD.bit.DATA_B = 1;

        // Wait for busy bit to clear.
        while(CanaRegs.CAN_IF2CMD.bit.Busy)
        {
        }

        // Read out the data from the CAN registers.
        uint16_t index;
        for(index = 0; index < 8; index++)
        {
            switch(index)
            {
                case 0:
                    rx_data[index] = CanaRegs.CAN_IF2DATA.bit.Data_0;
                break;
                case 1:
                    rx_data[index] = CanaRegs.CAN_IF2DATA.bit.Data_1;
                break;
                case 2:
                    rx_data[index] = CanaRegs.CAN_IF2DATA.bit.Data_2;
                break;
                case 3:
                    rx_data[index] = CanaRegs.CAN_IF2DATA.bit.Data_3;
                break;
                case 4:
                    rx_data[index] = CanaRegs.CAN_IF2DATB.bit.Data_4;
                break;
                case 5:
                    rx_data[index] = CanaRegs.CAN_IF2DATB.bit.Data_5;
                break;
                case 6:
                    rx_data[index] = CanaRegs.CAN_IF2DATB.bit.Data_6;
                break;
                case 7:
                    rx_data[index] = CanaRegs.CAN_IF2DATB.bit.Data_7;
                break;
            }
        }

        status = true;
    /*}
    else
    {
        status = false;
    }*/
    // Clear New Data Flag
    CanaRegs.CAN_IF2CMD.bit.TxRqst = 1;

    return(status);
}

Thanks

Damien

over 2 years ago

0 Joseph Casuga over 2 years ago

TI__Mastermind 34785 points

Hi Damien,

Can you clarify a few items? I assume you are not using interrupts to trigger frame reception. Comment in your above code (line 55) shows /// Receive message but succeeding codes seem that it is configuring a message object. There is a function read_CAN_message() but the checks for NewDat is commented out. How are you checking for the occurrence of new data for mailbox 2?

Regards,

Joseph

0 DAMIEN CHARNAY over 2 years ago in reply to Joseph Casuga

Intellectual 280 points

Hi Joseph,

You are reason I want use polling mode to trigger flames reception not interrupt. My comment at line 55 isn't appropriate it's a configuration of mail box for receive message. Mail box 1 i's configure for transmit message and isn't show here because it work and mail box 2 for reception.

I have test occurrence of new data for mail box2 with can_ndat_21 line 113 but this register i's always at 0 so I think no frame at reception has trigger by mask Filter no ?

If I don't t'est this one un read function, only verify candata register for one mail box configuration it will be work no ? When I'll configure more mail box for receive, this detection will be make.

My mail box 2 is in good configuration for receive message ?

I don't understand why can_ndat_21 equal 0 ? Trigger don't work I suppose.

Thanks

Damien

0 Joseph Casuga over 2 years ago in reply to DAMIEN CHARNAY

TI__Mastermind 34785 points

Hi Damien,

Can you move the the statements:

CanaRegs.CAN_IF2CMD.bit.DATA_A = 1;
CanaRegs.CAN_IF2CMD.bit.DATA_B = 1;

that is currently in receive_CAN_message earlier in routines where you have defined message object 2 to see if that works? I do not see these bits set in the IF2CMD register in the snapshot that you sent.

Regards,

Joseph

0 DAMIEN CHARNAY over 2 years ago in reply to Joseph Casuga

Intellectual 280 points

Hi Joseph,

I'm making progress in my debugging, but I'm stuck on a problem. I'm still configured with a sending frame with ID 0x100 (µC -> PC) and another frame with ID 0x010 (PC -> µC). I want to see in the CAN_IF1DATx register the data sent on the frame with ID 0x100 and see the data sent from the PC with ID 0x010 in a second CAN_IF2DAT buffer. But in debugger mode I see in CAN_IF1DAT and in CAN_IF2DAT the same data transmitted on the ID 0x100 in Tx. I do not access the data of the frame 0x010 in Can_rx.
Why don't I see my data from Can_Rx in CAN_IF2DAT? I certainly made a mistake on the configuration ?
I defined CAN_IF1CMD.bit.DIR = 1 (transmit direction)
                 CAN_IF1ARB.bit.Dir = 1 (transmit direction)
                 CAN_IF1ARB.bit.ID = 0x100 << 18
                 CAN_IF1CMD.bit.MSG_NUM = 1

                 CAN_IF1CMD DIR = 0 (receive direction)
                 CAN_IF1ARB.bit.Dir = 0 (receive direction)
                 CAN_IF1ARB.bit.ID = 0x010 << 18
                 CAN_IF1CMD.bit.MSG_NUM = 2

I don't see the problem, can you please help me?

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#include "f28002x_device.h"
#include "HPTS100_can.h"
uint16_t rx_data[8];
void can_init(void)
{
    EALLOW;
    /// Configure CANA_RX
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;     /// Disable the pullup on GPIO3
    GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 3;    /// To define mux position, mux position equal GPAGMUX(2bits) - GPAMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2;    /// GPIO3 = CANA_RX, see pin attributes documentation for mux position.
    GpioCtrlRegs.GPADIR.bit.GPIO3 = 0;     /// GPIO3 = input
    GpioCtrlRegs.GPAINV.bit.GPIO3 = 0;   /// Not inverted GPIO input
    /// Configure CANA_TX
    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;     /// Disable the pullup on GPIO2
    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;     /// GPIO2 = output
    GpioCtrlRegs.GPAODR.bit.GPIO2 = 0;     /// Normal output not open drain
    GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0;   /// Synchronous
    GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 3;   /// To define mux position, mux position equal GPBGMUX(2bits) - GPBMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
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#include "f28002x_device.h"
#include "HPTS100_can.h"

uint16_t rx_data[8];

void can_init(void)
{
    EALLOW;
    /// Configure CANA_RX
    GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1;     /// Disable the pullup on GPIO3
    GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 3;    /// To define mux position, mux position equal GPAGMUX(2bits) - GPAMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2;    /// GPIO3 = CANA_RX, see pin attributes documentation for mux position.
    GpioCtrlRegs.GPADIR.bit.GPIO3 = 0;     /// GPIO3 = input
    GpioCtrlRegs.GPAINV.bit.GPIO3 = 0;   /// Not inverted GPIO input

    /// Configure CANA_TX
    GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1;     /// Disable the pullup on GPIO2
    GpioCtrlRegs.GPADIR.bit.GPIO2 = 1;     /// GPIO2 = output
    GpioCtrlRegs.GPAODR.bit.GPIO2 = 0;     /// Normal output not open drain
    GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 0;   /// Synchronous
    GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 3;   /// To define mux position, mux position equal GPBGMUX(2bits) - GPBMUX(2bits) 0 to 15 number, here mux position equal 14 so GPAGMUX1 = 11b and GPAMUX1 = 10b.
    GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2;    /// GPIO2 = CANA_TX, see pin attributes documentation  for mux position.
    /// Place CAN controller in init state, regardless of previous state.
    /// This will put controller in idle, and allow the message object RAM to be programmed.
    /// CAN module ignore bus activity during configuration.
    CanaRegs.CAN_CTL.bit.Init = 1;
    /// The CPU has write access to the configuration register.
    CanaRegs.CAN_CTL.bit.CCE = 1;
    /// Clock and timing bit configuration
    ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0;
    /// Set up the bit rate for the CAN bus, with 250kbit/s.
    /// Bit time (Tq) = 8
    /// Bit clock prescaler = 49dec = 0x31
    /// Propagation segment (Tq) = 1
    /// Phase segment 1 (Tq) = 3dec = 0x3
    /// Phase segment 2 (Tq) = 2dec = 0x2
    /// Synchronization jump width (Tq) = 2dec = 0x2
    /// Sampling point = 62.5%
    /// Oscillator tolerance = 1.48%
    /// Set Baud rate prescaler.
    CanaRegs.CAN_BTR.bit.BRP = 0x31;
    /// Synchronization jump width.
    CanaRegs.CAN_BTR.bit.SJW = 0x2;
    /// Time segment before the sample point.
    CanaRegs.CAN_BTR.bit.TSEG1 = 0x3;
    /// Time segment after the sample point.
    CanaRegs.CAN_BTR.bit.TSEG2 = 0x2;

    /// CAN module processes messages normally
    CanaRegs.CAN_CTL.bit.Init = 0;

    setupMessageObject(1, 0x100, MSG_OBJ_TYPE_TRANSMIT);
    setupMessageObject(2, 0x010, MSG_OBJ_TYPE_RECEIVE);
    EDIS;
}

void setupMessageObject(uint32_t objID, uint32_t msgID, msgObjType msgType)
{
    if(msgType == MSG_OBJ_TYPE_TRANSMIT)
    {
        /// Use Shadow variable for IF1CMD. IF1CMD should be written to in single 32-bit write.
        union CAN_IF1CMD_REG CAN_IF1CMD_SHADOW;
        /// Wait for busy bit to clear.
        while(CanaRegs.CAN_IF1CMD.bit.Busy)
        {
        }
        /// Clear and Write out the registers to program the message object.
        CAN_IF1CMD_SHADOW.all = 0;
        CanaRegs.CAN_IF1MSK.all = 0;
        CanaRegs.CAN_IF1ARB.all = 0;
        CanaRegs.CAN_IF1MCTL.all = 0;

        /// Set the Control, Mask, and Arb bit so that they get transferred to the message object.
        /// The message control bits will be transferred from the IF1 register set to the message object.
        CAN_IF1CMD_SHADOW.bit.Control = 1;
        /// The arbitration bits will be transferred from the IF1 register set to the message object.
        CAN_IF1CMD_SHADOW.bit.Arb = 1;
        /// The mask bits (Identifier mask + Mdir + MXtd) will be transferred from the IF1 register to the message object.
        CAN_IF1CMD_SHADOW.bit.Mask = 1;
        /// Transfer direction is transferred to the message object : write
        CAN_IF1CMD_SHADOW.bit.DIR = 1;

        /// Transmit direction
        CanaRegs.CAN_IF1ARB.bit.Dir = 1;
        /// Set Message ID.
        CanaRegs.CAN_IF1ARB.bit.ID = (msgID << 18);
        /// Mail box is enabled.
        CanaRegs.CAN_IF1ARB.bit.MsgVal = 1;

        /// Set the data length since this is set for all transfers. This is also a single transfer and not a FIFO transfer so set EOB bit.
        /// Data frame has 8 data bytes
        CanaRegs.CAN_IF1MCTL.bit.DLC = 9;
        /// The message object is a single message object or the last message object in a FIFO buffer.
        CanaRegs.CAN_IF1MCTL.bit.EoB = 1;

        /// Transfer data to message object RAM
        CAN_IF1CMD_SHADOW.bit.MSG_NUM = objID;
        CanaRegs.CAN_IF1CMD.all = CAN_IF1CMD_SHADOW.all;
    }
    else
    {
        /// Use Shadow variable for IF1CMD. IF1CMD should be written to in single 32-bit write.
        union CAN_IF2CMD_REG CAN_IF2CMD_SHADOW;
        /// Wait for busy bit to clear.
        while(CanaRegs.CAN_IF2CMD.bit.Busy)
        {
        }
        /// Clear and Write out the registers to program the message object.
        CAN_IF2CMD_SHADOW.all = 0;
        CanaRegs.CAN_IF2MSK.all = 0;
        CanaRegs.CAN_IF2ARB.all = 0;
        CanaRegs.CAN_IF2MCTL.all = 0;

        /// Set the Control, Mask, and Arb bit so that they get transferred to the message object.
        /// The message control bits will be transferred from the IF1 register set to the message object.
        CAN_IF2CMD_SHADOW.bit.Control = 1;
        /// The arbitration bits will be transferred from the IF1 register set to the message object.
        CAN_IF2CMD_SHADOW.bit.Arb = 1;
        /// The mask bits (Identifier mask + Mdir + MXtd) will be transferred from the IF1 register to the message object.
        CAN_IF2CMD_SHADOW.bit.Mask = 1;
        /// Transfer direction is transferred to the message object : read
        CAN_IF2CMD_SHADOW.bit.DIR = 0;

        /// Receive direction
        CanaRegs.CAN_IF2ARB.bit.Dir = 0;
        /// Set Message ID.
        CanaRegs.CAN_IF2ARB.bit.ID = (msgID << 18);
        /// Mail box is enabled.
        CanaRegs.CAN_IF2ARB.bit.MsgVal = 1;

        /// Set the data length since this is set for all transfers. This is also a single transfer and not a FIFO transfer so set EOB bit.
        /// Data frame has 8 data bytes
        CanaRegs.CAN_IF2MCTL.bit.DLC = 9;
        /// The message object is a single message object or the last message object in a FIFO buffer.
        CanaRegs.CAN_IF2MCTL.bit.EoB = 1;

        /// Transfer data to message object RAM
        CAN_IF2CMD_SHADOW.bit.MSG_NUM = objID;
        CanaRegs.CAN_IF2CMD.all = CAN_IF2CMD_SHADOW.all;
    }
}

void send_CAN_message()
{
    // Use Shadow variable for IF1CMD. IF1CMD should be written to in single 32-bit write.
    union CAN_IF1CMD_REG CAN_IF1CMD_SHADOW;

    // Wait for busy bit to clear.
    while(CanaRegs.CAN_IF1CMD.bit.Busy)
    {
    }

    CanaRegs.CAN_IF1DATA.bit.Data_0 = 0x1;
    CanaRegs.CAN_IF1DATA.bit.Data_1 = 0x2;
    CanaRegs.CAN_IF1DATA.bit.Data_2 = 0x3;
    CanaRegs.CAN_IF1DATA.bit.Data_3 = 0x4;
    CanaRegs.CAN_IF1DATB.bit.Data_4 = 0x5;
    CanaRegs.CAN_IF1DATB.bit.Data_5 = 0x6;
    CanaRegs.CAN_IF1DATB.bit.Data_6 = 0x7;
    CanaRegs.CAN_IF1DATB.bit.Data_7 = 0x8;

    // Set Direction to write and set DATA-A/DATA-B to be transfered to message object
    CAN_IF1CMD_SHADOW.all = 0;
    CAN_IF1CMD_SHADOW.bit.DIR = 1;
    CAN_IF1CMD_SHADOW.bit.DATA_A = 1;
    CAN_IF1CMD_SHADOW.bit.DATA_B = 1;

    // Set Tx Request Bit
    CAN_IF1CMD_SHADOW.bit.TXRQST = 1;

    // Transfer the message object to the message object specified by objID.
    CAN_IF1CMD_SHADOW.bit.MSG_NUM = 1;//obj id;
    CanaRegs.CAN_IF1CMD.all = CAN_IF1CMD_SHADOW.all;
}

void receive_CAN_message()
{
    //CanaRegs.CAN_IF2CMD.bit.Arb = 1;
    CanaRegs.CAN_IF2CMD.all = 0;
    CanaRegs.CAN_IF2CMD.bit.Control = 1;
    CanaRegs.CAN_IF2CMD.bit.DATA_A = 1;
    CanaRegs.CAN_IF2CMD.bit.DATA_B = 1;
    /// Obj ID
    CanaRegs.CAN_IF2CMD.bit.MSG_NUM = 2;

    // Wait for busy bit to clear.
    while(CanaRegs.CAN_IF2CMD.bit.Busy)
    {
    }

    if(CanaRegs.CAN_IF2MCTL.bit.NewDat == 1)
    {
        rx_data[0] = CanaRegs.CAN_IF2DATA.bit.Data_0;
        rx_data[1] = CanaRegs.CAN_IF2DATA.bit.Data_1;
        rx_data[2] = CanaRegs.CAN_IF2DATA.bit.Data_2;
        rx_data[3] = CanaRegs.CAN_IF2DATA.bit.Data_3;
        rx_data[4] = CanaRegs.CAN_IF2DATB.bit.Data_4;
        rx_data[5] = CanaRegs.CAN_IF2DATB.bit.Data_5;
        rx_data[6] = CanaRegs.CAN_IF2DATB.bit.Data_6;
        rx_data[7] = CanaRegs.CAN_IF2DATB.bit.Data_7;
    }
    CanaRegs.CAN_IF2CMD.bit.TxRqst = 1;
    // Transfer the message object to the message object IF register.
    //CanaRegs.CAN_IF2CMD.bit.MSG_NUM = 2;
}

Thanks

Damien

0 DAMIEN CHARNAY over 2 years ago in reply to DAMIEN CHARNAY

Intellectual 280 points

best screenshots

0 Joseph Casuga over 2 years ago in reply to DAMIEN CHARNAY

TI__Mastermind 34785 points

Hi Damien,

Good to hear that you are making good progress with your code. I see that you are starting to receive CAN frames. On your attached code, you have reference to SHADOW registers. Our examples for F28002x are currently written using driverlib codes and it seems like you are using some old code referring to SHADOW registers from a different type of CAN (eCAN). There are no SHADOW registers in F28002x DCAN. I just want to make sure that you are programming the correct CAN registers. Can you clarify what these shadow registers are on F28002x that you have used?

Thanks,

Joseph

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F280025C: CAN receive frame configuration, transmit is ok (polling mode)