Hello TI Support Team,
In our previous designs with F280049, we use many times an external clock to supply 100Mhz to the GPIO19 Pin. The main purpose is reduce the current consumption with NOT using the PLL. That works very well so far.
But on newer devices I noticed a new electrical parameter is listed:
According to this parameter, maximum external clock frequncy is 60Mhz. This is half of the maximim Sysclk of F280039.
My question is, are newer devices rated lower then F280049 regarding to clock input capability? What happens if I drive this pin with 120Mhz? What is the limiting factor here?
Should I wory about our older designs? Did we drive this pin out of spec?
Regards,
Özgür Derin
