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TMS320F28335: CAN-A or CAN-B does not work intermittently.

Minseung Kim
Prodigy 10 points

Part Number: TMS320F28335

CAN-A or CAN-B does not work intermittently.

I am using TMS320F28335 to communicate with other boards.
It communicates with 8 boards through CAN-A.
And it communicates with 8 boards through CAN-B.

When there is a symptom of intermittent stop during CAN communication, when checking the CANGIF0 register, it was as follows.

CANGIF0 Register

name MTOF0 TCOF0 GMIF0 AAIF0 WDIF0 WUIF0 RMLIF0 BOIF0 EPIF0 WLIF0 Reserved Reserved Reserved MIV0.4 MIV0.3 MIV0.2 MIV0.1 MIV0.0
cana 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
canb 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 1 1
From the above situation, it seems that the interrupt is not cleared in mailbox 19.
When the CANRMP register was read in this situation, all bits were cleared to 0.
What do I need to check to resolve this issue?
  • 0
    Prodigy 10 points

    Also upload the source code.

    void InitCana(void) // Initialize eCAN-A module
    {

    /* Create a shadow register structure for the CAN control registers. This is
    needed, since only 32-bit access is allowed to these registers. 16-bit access
    to these registers could potentially corrupt the register contents or return
    false data. This is especially true while writing to/reading from a bit
    (or group of bits) among bits 16 - 31 */

    struct ECAN_REGS ECanaShadow;

    InitECanaGpio();

    EALLOW; // EALLOW enables access to protected bits

    /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

    /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
    // HECC mode also enables time-stamping feature

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    /* Initialize all bits of 'Master Control Field' to zero */
    // Some bits of MSGCTRL register come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.

    ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */

    ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */

    ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;


    /* Configure bit timing parameters for eCANA*/
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
    /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
    See Note at End of File */
    ECanaShadow.CANBTC.bit.BRPREG = 9; // 4 -> 9(500Kbps) -> 19(250Kbps) -> 39(125Kbps)
    ECanaShadow.CANBTC.bit.TSEG2REG = 2; // 2
    ECanaShadow.CANBTC.bit.TSEG1REG = 10; // 10
    #endif
    #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
    /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
    See Note at End of File */
    ECanaShadow.CANBTC.bit.BRPREG = 4;
    ECanaShadow.CANBTC.bit.TSEG2REG = 1;
    ECanaShadow.CANBTC.bit.TSEG1REG = 6;
    #endif


    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..

    /* Disable all Mailboxes */
    ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs

    EDIS;
    }

    void InitCanb(void) // Initialize eCAN-B module
    {
    /* Create a shadow register structure for the CAN control registers. This is
    needed, since only 32-bit access is allowed to these registers. 16-bit access
    to these registers could potentially corrupt the register contents or return
    false data. This is especially true while writing to/reading from a bit
    (or group of bits) among bits 16 - 31 */

    struct ECAN_REGS ECanbShadow;

    InitECanbGpio();

    EALLOW; // EALLOW enables access to protected bits

    /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
    ECanbShadow.CANTIOC.bit.TXFUNC = 1;
    ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

    ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
    ECanbShadow.CANRIOC.bit.RXFUNC = 1;
    ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

    /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
    ECanbShadow.CANMC.bit.SCB = 1;
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    /* Initialize all bits of 'Master Control Field' to zero */
    // Some bits of MSGCTRL register come up in an unknown state. For proper operation,
    // all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

    // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
    // as a matter of precaution.

    ECanbRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */

    ECanbRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */

    ECanbRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanbRegs.CANGIF1.all = 0xFFFFFFFF;


    /* Configure bit timing parameters for eCANB*/

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
    ECanbShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
    {
    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
    } while(ECanbShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be cleared..

    ECanbShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ) // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
    /* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
    See Note at end of file */
    ECanbShadow.CANBTC.bit.BRPREG = 9;
    ECanbShadow.CANBTC.bit.TSEG2REG = 2;
    ECanbShadow.CANBTC.bit.TSEG1REG = 10;
    #endif
    #if (CPU_FRQ_100MHZ) // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
    /* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
    See Note at end of file */
    ECanbShadow.CANBTC.bit.BRPREG = 4;
    ECanbShadow.CANBTC.bit.TSEG2REG = 1;
    ECanbShadow.CANBTC.bit.TSEG1REG = 6;
    #endif

    ECanbShadow.CANBTC.bit.SAM = 1;
    ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
    ECanbShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
    {
    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
    } while(ECanbShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..

    /* Disable all Mailboxes */
    ECanbRegs.CANME.all = 0; // Required before writing the MSGIDs

    EDIS;
    }

    void InitMailBoxA(void)
    {
    struct ECAN_REGS ECanaShadow;

    /************************************
    * Can A Init *
    ************************************/
    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the messgeId field of TRANSMIT mailboxes MBOX0 - 15
    // 펌웨어 버전 데이터 - MBOX0로 고정.
    ECanaMboxes.MBOX0.MSGID.all = 0x80000000 + CAN_M2C_FWDCMD_MSGID;
    ECanaMboxes.MBOX1.MSGID.all = 0x80000000 + CAN_M2C_CMD_BASEID;

    // Write to the messgeId field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0xC0000000 + CAN_C2M_MONI_BASEID;
    ECanaLAMRegs.LAM16.all = 0x8000FFFF;
    ECanaMboxes.MBOX17.MSGID.all = 0xC0000000 + CAN_C2M_ERR_BASEID;
    ECanaLAMRegs.LAM17.all = 0x8000FFFF;
    ECanaMboxes.MBOX18.MSGID.all = 0xC0000000 + CAN_C2M_STAT_BASEID;
    ECanaLAMRegs.LAM18.all = 0x8000FFFF;
    ECanaMboxes.MBOX19.MSGID.all = 0xC0000000 + CAN_C2M_FIRM_BASEID;
    ECanaLAMRegs.LAM19.all = 0x8000FFFF;
    ECanaMboxes.MBOX20.MSGID.all = 0xC0000000 + CAN_C2M_TRAY_BASEID;
    ECanaLAMRegs.LAM20.all = 0x8000FFFF;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    // ECanaRegs.CANMD.all = 0xFFFF0000;
    ECanaRegs.CANMD.all = 0x001F0000; // 오동작 방지를 위해 쓰지 않는 박스는 TX로 설정.

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    // ECanaRegs.CANME.all = 0x07FF07FF;
    ECanaRegs.CANME.all = 0x001F0003; // 오동작 방지를 위해 쓰지 않는 박스는 Diable로 설정

    // Specify that 8 bits will be sent/received
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;

    ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX22.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX23.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX24.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8;
    // ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    EALLOW;
    // ECanaRegs.CANMIM.all = 0x07FF0000;
    ECanaRegs.CANMIM.all = 0x001F0000;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.DBO = 1; // 0:Big Endian, 1:Little Endian
    ECanaShadow.CANMC.bit.ABO = 1; // Auto bus on
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaRegs.CANMIL.all = 0x00000000;
    // ECanaRegs.CANGAM.all = 0xFFFFFFFF;

    ECanaRegs.CANGIM.bit.I0EN = 1; // Interrupt 0 Enable
    EDIS;

    }

    //#pragma CODE_SECTION(InitMailBoxB, "ramfuncs");
    void InitMailBoxB(void)
    {
    struct ECAN_REGS ECanbShadow;
    /************************************
    * Can B Init *
    ************************************/
    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the messgeId field of TRANSMIT mailboxes MBOX0 - 15

    ECanbMboxes.MBOX0.MSGID.all = 0x80000000 + CAN_M2C_FWDCMD_MSGID;
    ECanbMboxes.MBOX1.MSGID.all = 0x80000000 + CAN_M2C_CMD_BASEID;
    // ECanbMboxes.MBOX2.MSGID.all = 0x80000402;
    // ECanbMboxes.MBOX3.MSGID.all = 0x80000403;
    // ECanbMboxes.MBOX4.MSGID.all = 0x80000404;
    // ECanbMboxes.MBOX5.MSGID.all = 0x80000405;
    // ECanbMboxes.MBOX6.MSGID.all = 0x80595306;
    // ECanbMboxes.MBOX7.MSGID.all = 0x80595307;
    // ECanbMboxes.MBOX8.MSGID.all = 0x80595308;
    // ECanbMboxes.MBOX9.MSGID.all = 0x80595309;
    // ECanbMboxes.MBOX10.MSGID.all = 0x8059530A;

    // Write to the messgeId field of RECEIVE mailboxes MBOX16 - 31
    ECanbMboxes.MBOX16.MSGID.all = 0xC0000000 + CAN_C2M_MONI_BASEID;
    ECanbLAMRegs.LAM16.all = 0x8000FFFF;
    ECanbMboxes.MBOX17.MSGID.all = 0xC0000000 + CAN_C2M_ERR_BASEID;
    ECanbLAMRegs.LAM17.all = 0x8000FFFF;
    ECanbMboxes.MBOX18.MSGID.all = 0xC0000000 + CAN_C2M_STAT_BASEID;
    ECanbLAMRegs.LAM18.all = 0x8000FFFF;
    ECanbMboxes.MBOX19.MSGID.all = 0xC0000000 + CAN_C2M_FIRM_BASEID;
    ECanbLAMRegs.LAM19.all = 0x8000FFFF;
    ECanbMboxes.MBOX20.MSGID.all = 0xC0000000 + CAN_C2M_TRAY_BASEID;
    ECanbLAMRegs.LAM20.all = 0x8000FFFF;

    // ECanbMboxes.MBOX16.MSGID.all = 0xC0010000;
    // ECanbLAMRegs.LAM16.all = 0x8000FFFF;
    // ECanbMboxes.MBOX17.MSGID.all = 0xC0020000;
    // ECanbLAMRegs.LAM17.all = 0x800000FF;
    // ECanbMboxes.MBOX18.MSGID.all = 0xC0030000;
    // ECanbLAMRegs.LAM18.all = 0x8000FFFF;
    // ECanbMboxes.MBOX19.MSGID.all = 0x90595303;
    // ECanbMboxes.MBOX20.MSGID.all = 0x90595304;
    // ECanbMboxes.MBOX21.MSGID.all = 0x90595305;
    // ECanbMboxes.MBOX22.MSGID.all = 0x90595306;
    // ECanbMboxes.MBOX23.MSGID.all = 0x90595307;
    // ECanbMboxes.MBOX24.MSGID.all = 0x90595308;
    // ECanbMboxes.MBOX25.MSGID.all = 0x90595309;
    // ECanbMboxes.MBOX26.MSGID.all = 0x9059530A;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    // ECanbRegs.CANMD.all = 0xFFFF0000;
    ECanbRegs.CANMD.all = 0x001F0000; // 오동작 방지를 위해 쓰지 않는 박스는 TX로 설정.

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    // ECanbRegs.CANME.all = 0x07FF07FF;
    ECanbRegs.CANME.all = 0x001F0003; // 오동작 방지를 위해 쓰지 않는 박스는 Diable로 설정

    // Specify that 8 bits will be sent/received
    ECanbMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX10.MSGCTRL.bit.DLC = 8;

    ECanbMboxes.MBOX16.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX17.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX18.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX20.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX21.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX22.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX23.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX24.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    EALLOW;
    // ECanbRegs.CANMIM.all = 0x07FF0000;
    ECanbRegs.CANMIM.all = 0x001F0000;

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
    ECanbShadow.CANMC.bit.DBO = 1; // 0:Big Endian, 1:Little Endian
    ECanbShadow.CANMC.bit.ABO = 1; // Auto bus on
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbRegs.CANMIL.all = 0x00000000;
    // ECanaRegs.CANGAM.all = 0xFFFFFFFF;

    ECanbRegs.CANGIM.bit.I0EN = 1; // Interrupt 0 Enable
    EDIS;
    }

    interrupt void ECana_Rx_isr(void)
    {
    struct ECAN_REGS ECanaShadow;
    CANARXIsrCount++;
    ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;
    CanaRxDataPush(&ECanaShadow);
    ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;
    PieCtrlRegs.PIEACK.bit.ACK9 = 1;
    }

    interrupt void ECanb_Rx_isr(void)
    {
    struct ECAN_REGS ECanbShadow;
    CANBRXIsrCount++;
    ECanbShadow.CANRMP.all = ECanbRegs.CANRMP.all;
    CanbRxDataPush(&ECanbShadow);
    ECanbRegs.CANRMP.all = ECanbShadow.CANRMP.all;
    PieCtrlRegs.PIEACK.bit.ACK9 = 1;
    }

  • 0 in reply to Minseung Kim
    TI__Guru* 95315 points

    Minseung,

                  Debugging your code is not something we can support on the forum. Please ensure your problem is not related to the " eCAN: Unexpected Cessation of Transmit Operation" advisory in page 11 of www.ti.com/lit/SPRZ272.

    Not sure what you mean by " intermittent stop during CAN communication". Is it the transmit operation or the receive operation that is stopping?  If the interrupt flag is not being cleared, please refer to the examples in www.ti.com/lit/SPRA876. There are examples that show you how to handle interrupts.