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I have 2 ccs projects, Application and Bootloader.
Booatloader Flash memory is from 0x080000 to 0x081FFF
Application Flash memory is from 0x082000 to 0x08FFFF
I successfully merged them using -load_image and created a single hex file for them.
but after i load it in the control card, it can jump from bootloader main to application main loop but the .cinit of application did not initialized.
Application side cannot read datas in the .cinit of application.
the one i monitor is the .cinit.Cla1ToCpuMsgRam.load of application.map
Please see attached link.cmd and map files of bootloader and application.
Can you help me with this?
Application Flash Lnk cmd
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x082000, length = 0x00004
RAMM0 : origin = 0x0000F3, length = 0x00030D
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS12 : origin = 0x008800, length = 0x001000
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
//RAMLS7 : origin = 0x00B800, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
// FLASH_BANK0_BOOT : origin = 0x080000, length = 0x002000 /* on-chip Flash */
// FLASH_BANK0_APP : origin = 0x082004, length = 0x00DFFB, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC0 : origin = 0x080000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC2 : origin = 0x082004, length = 0x000FFC, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC78 : origin = 0x087000, length = 0x002000, fill = 0xFFFF /* on-chip Flash */
// FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
// FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000, fill = 0xFFFF /* on-chip Flash */
/* BANK 1 */
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
//RAMLS1 : origin = 0x008800, length = 0x000800
//RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN PAGE = 0, ALIGN(4)
.text : >>FLASH_BANK0_SEC2 | FLASH_BANK0_SEC6 | FLASH_BANK0_SEC78 | FLASH_BANK0_SEC9 | FLASH_BANK0_SEC10 | FLASH_BANK0_SEC11 | FLASH_BANK0_SEC12 | FLASH_BANK0_SEC13 | FLASH_BANK0_SEC14 | FLASH_BANK0_SEC15, PAGE = 0, ALIGN(4)
.cinit : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
.stack : > RAMM1 PAGE = 1
.switch : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
.init_array : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS5, PAGE = 1
.bss:cio : > RAMLS5, PAGE = 1
.data : >>RAMLS6 | RAMLS7 | RAMLS5, PAGE = 1
.sysmem : > RAMLS6, PAGE = 1
.const : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
.ebss : >>RAMLS5 | RAMLS6, PAGE = 1
.esysmem : > RAMLS6, PAGE = 1
.cio : > RAMLS5, PAGE = 1
.econst : > FLASH_BANK0_SEC4, PAGE = 0, ALIGN(4)
#endif
ramgs0 : > RAMGS2, PAGE = 1
ramgs1 : > RAMGS3, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
/* Ram functions */
#if defined(__TI_EABI__)
.TI.ramfunc : LOAD = FLASH_BANK0_SEC4,
RUN = RAMLS12
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE( RamfuncsLoadSize ),
LOAD_END( RamfuncsLoadEnd ),
RUN_START( RamfuncsRunStart ),
RUN_SIZE( RamfuncsRunSize ),
RUN_END( RamfuncsRunEnd ),
PAGE = 0, ALIGN(4)
#else
.TI.ramfunc : LOAD = FLASH_BANK0_SEC4,
RUN = RAMLS12
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE( _RamfuncsLoadSize ),
LOAD_END( _RamfuncsLoadEnd ),
RUN_START( _RamfuncsRunStart ),
RUN_SIZE( _RamfuncsRunSize ),
RUN_END( _RamfuncsRunEnd ),
PAGE = 0, ALIGN(4)
#endif
/* Allocate fixed point Math - with Gen3 devices, IQMath is not required */
IQmath : > FLASH_BANK0_SEC6, PAGE = 0
IQmathTables : > FLASH_BANK0_SEC6, PAGE = 0 /* , TYPE = NOLOAD */
/* Floating point Math */
// FPUmathTables : > RAMGS3, PAGE =1
FPUmathTables : > FLASH_BANK0_SEC4, PAGE = 0
/* CLA linker */
/* CLA specific sections */
#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASH_BANK0_SEC5 | FLASH_BANK0_SEC6,
RUN = RAMLS0,
LOAD_START(Cla1ProgLoadStart),
RUN_START( Cla1ProgRunStart ),
LOAD_SIZE( Cla1ProgLoadSize ),
PAGE = 0, ALIGN(4)
#else
Cla1Prog : LOAD = FLASH_BANK0_SEC5,
RUN = RAMLS0,
LOAD_START(_Cla1ProgLoadStart),
RUN_START( _Cla1ProgRunStart ),
LOAD_SIZE( _Cla1ProgLoadSize ),
PAGE = 0, ALIGN(4)
#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
#if 0
CLA1mathTables : LOAD = FLASH_BANK0_SEC5,
RUN = RAMLS7,
LOAD_START( Cla1mathTablesLoadStart),
LOAD_END( Cla1mathTablesLoadEnd ),
RUN_START( Cla1mathTablesRunStart ),
LOAD_SIZE( Cla1mathTablesLoadSize ),
PAGE = 0, ALIGN(4)
#endif
.scratchpad : > RAMLS7, PAGE = 1
.bss_cla : > RAMLS7, PAGE = 1
controlVariables : > RAMLS7, PAGE = 1
Cla1DataRam : > RAMLS7, PAGE = 1
cla_shared : > RAMLS7, PAGE = 1
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH_BANK0_SEC5,
RUN = RAMLS12,
RUN_START( Cla1ConstRunStart ),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE( Cla1ConstLoadSize ),
PAGE = 0, ALIGN(4)
#else
.const_cla : LOAD = FLASH_BANK0_SEC5,
RUN = RAMLS12,
RUN_START( _Cla1ConstRunStart ),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE( _Cla1ConstLoadSize ),
PAGE = 0, ALIGN(4)
#endif
}
/*! @} */
Bootloader Flash Lnk cmd
//
// Keep the _bankSelect symbol
//
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000008, length = 0x0003F8
RAMLS0 : origin = 0x008000, length = 0x000800 /* 2kWord, for CLA code */
RAMLS1 : origin = 0x008800, length = 0x000800
//RAMLS3 : origin = 0x009800, length = 0x000800
//RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS34 : origin = 0x009800, length = 0x001000
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
/* BANK 0 */
// FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
// FLASH_BANK0_SEC1 : origin = 0x081000, length = 0x001000 /* on-chip Flash */
FLASH_BOOT : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH_BANK0_SEC2 : origin = 0x082000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC3 : origin = 0x083000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC4 : origin = 0x084000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC5 : origin = 0x085000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC6 : origin = 0x086000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC7 : origin = 0x087000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC8 : origin = 0x088000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC9 : origin = 0x089000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC10 : origin = 0x08A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC11 : origin = 0x08B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC12 : origin = 0x08C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC13 : origin = 0x08D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC14 : origin = 0x08E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK0_SEC15 : origin = 0x08F000, length = 0x001000 /* on-chip Flash */
/* BANK 1 */
FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC2 : origin = 0x092000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC3 : origin = 0x093000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC4 : origin = 0x094000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC5 : origin = 0x095000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC6 : origin = 0x096000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC7 : origin = 0x097000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC8 : origin = 0x098000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC9 : origin = 0x099000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC10 : origin = 0x09A000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC11 : origin = 0x09B000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC12 : origin = 0x09C000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC13 : origin = 0x09D000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC14 : origin = 0x09E000, length = 0x001000 /* on-chip Flash */
FLASH_BANK1_SEC15 : origin = 0x09F000, length = 0x000FF0 /* on-chip Flash */
// FLASH_BANK1_SEC15_RSVD : origin = 0x09FFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000F1 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
// RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x002000
RAMGS1 : origin = 0x00E000, length = 0x002000
RAMGS2 : origin = 0x010000, length = 0x002000
RAMGS3 : origin = 0x012000, length = 0x001FF8
// RAMGS3_RSVD : origin = 0x013FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
// CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
// CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN PAGE = 0, ALIGN(4)
.text : >> FLASH_BOOT, PAGE = 0, ALIGN(4)
.cinit : > FLASH_BOOT, PAGE = 0, ALIGN(4)
.stack : > RAMM0 PAGE = 0
.switch : > FLASH_BOOT, PAGE = 0, ALIGN(4)
#if defined(__TI_EABI__)
.init_array : > FLASH_BOOT, PAGE = 0, ALIGN(4)
.bss : > RAMLS34, PAGE = 0
.bss:output : > RAMLS34, PAGE = 0
.bss:cio : > RAMLS34, PAGE = 0
.data : >>RAMLS34, PAGE = 0
.sysmem : > RAMLS34, PAGE = 0
.const : > FLASH_BOOT, PAGE = 0, ALIGN(4)
#else
.pinit : > FLASH_BOOT, PAGE = 0, ALIGN(4)
.ebss : >>RAMLS34, PAGE = 0
.esysmem : > RAMLS34, PAGE = 0
.cio : > RAMLS34, PAGE = 0
.econst : > FLASH_BOOT, PAGE = 0, ALIGN(4)
#endif
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
/*
* Ram functions
* */
#if defined(__TI_EABI__)
GROUP
{
.TI.ramfunc
{-l F021_API_F28004x_FPU32_EABI.lib}
} LOAD = FLASH_BOOT,
RUN = RAMLS34
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE( RamfuncsLoadSize ),
LOAD_END( RamfuncsLoadEnd ),
RUN_START( RamfuncsRunStart ),
RUN_SIZE( RamfuncsRunSize ),
RUN_END( RamfuncsRunEnd ),
PAGE = 0, ALIGN(4)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Application Map
******************************************************************************
TMS320C2000 Linker PC v21.6.0
******************************************************************************
>> Linked Wed Feb 15 10:04:20 2023
OUTPUT FILE NAME: <application.out>
ENTRY POINT SYMBOL: "code_start" address: 00082000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
RAMM0 000000f3 0000030d 00000000 0000030d RWIX
RAMLS0 00008000 00000800 000007a0 00000060 RWIX
RAMLS12 00008800 00001000 00000134 00000ecc RWIX
RAMLS3 00009800 00000800 00000000 00000800 RWIX
RAMLS4 0000a000 00000800 00000000 00000800 RWIX
DCSM_OTP_Z1_LINKPOINT 00078000 0000000c 00000000 0000000c RWIX
DCSM_OTP_Z1_GPREG 0007800c 00000004 00000002 00000002 RWIX
DCSM_OTP_Z1_PSWDLOCK 00078010 00000004 00000004 00000000 RWIX
DCSM_OTP_Z1_CRCLOCK 00078014 00000004 00000004 00000000 RWIX
DCSM_OTP_Z1_BOOTCTRL 0007801c 00000004 00000002 00000002 RWIX
DCSM_ZSEL_Z1_P0 00078020 00000010 00000000 00000010 RWIX
DCSM_OTP_Z2_LINKPOINT 00078200 0000000c 00000000 0000000c RWIX
DCSM_OTP_Z2_GPREG 0007820c 00000004 00000000 00000004 RWIX
DCSM_OTP_Z2_PSWDLOCK 00078210 00000004 00000000 00000004 RWIX
DCSM_OTP_Z2_CRCLOCK 00078214 00000004 00000000 00000004 RWIX
DCSM_OTP_Z2_BOOTCTRL 0007821c 00000004 00000000 00000004 RWIX
DCSM_ZSEL_Z2_P0 00078220 00000010 00000000 00000010 RWIX
B1_DCSM_OTP_Z1_LINKPO 00078400 0000000c 00000000 0000000c RWIX
B1_DCSM_ZSEL_Z1_P0 00078420 00000010 00000000 00000010 RWIX
B1_DCSM_OTP_Z2_LINKPO 00078600 0000000c 00000000 0000000c RWIX
B1_DCSM_ZSEL_Z2_P0 00078620 00000010 00000000 00000010 RWIX
FLASH_BANK0_SEC0 00080000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC1 00081000 00001000 00000000 00001000 RWIX
BEGIN 00082000 00000004 00000002 00000002 RWIX
FLASH_BANK0_SEC2 00082004 00000ffc 00000ffc 00000000 RWIX ffff
FLASH_BANK0_SEC3 00083000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC4 00084000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC5 00085000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC6 00086000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC78 00087000 00002000 00002000 00000000 RWIX ffff
FLASH_BANK0_SEC9 00089000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC10 0008a000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC11 0008b000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC12 0008c000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC13 0008d000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC14 0008e000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK0_SEC15 0008f000 00001000 00001000 00000000 RWIX ffff
FLASH_BANK1_SEC0 00090000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC1 00091000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC2 00092000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC3 00093000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC4 00094000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC5 00095000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC6 00096000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC7 00097000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC8 00098000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC9 00099000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC10 0009a000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC11 0009b000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC12 0009c000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC13 0009d000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC14 0009e000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC15 0009f000 00000ff0 00000000 00000ff0 RWIX
RESET 003fffc0 00000002 00000000 00000002 RWIX
PAGE 1:
BOOT_RSVD 00000002 000000f1 00000001 000000f0 RWIX
RAMM1 00000400 000003f8 000003f8 00000000 RWIX
ADCA_RESULT 00000b00 00000020 00000000 00000020 RWIX
ADCB_RESULT 00000b20 00000020 00000000 00000020 RWIX
ADCC_RESULT 00000b40 00000020 00000000 00000020 RWIX
CPU_TIMER0 00000c00 00000008 00000000 00000008 RWIX
CPU_TIMER1 00000c08 00000008 00000000 00000008 RWIX
CPU_TIMER2 00000c10 00000008 00000000 00000008 RWIX
PIE_CTRL 00000ce0 00000020 00000000 00000020 RWIX
PIE_VECT 00000d00 00000200 00000000 00000200 RWIX
DMA 00001000 00000200 00000000 00000200 RWIX
CLA1 00001400 00000080 00000000 00000080 RWIX
CLA1_MSGRAMLOW 00001480 00000080 00000014 0000006c RWIX
CLA1_MSGRAMHIGH 00001500 00000080 00000024 0000005c RWIX
EPWM1 00004000 00000100 00000000 00000100 RWIX
EPWM2 00004100 00000100 00000000 00000100 RWIX
EPWM3 00004200 00000100 00000000 00000100 RWIX
EPWM4 00004300 00000100 00000000 00000100 RWIX
EPWM5 00004400 00000100 00000000 00000100 RWIX
EPWM6 00004500 00000100 00000000 00000100 RWIX
EPWM7 00004600 00000100 00000000 00000100 RWIX
EPWM8 00004700 00000100 00000000 00000100 RWIX
EQEP1 00005100 00000040 00000000 00000040 RWIX
EQEP2 00005140 00000040 00000000 00000040 RWIX
ECAP1 00005200 00000040 00000000 00000040 RWIX
ECAP2 00005240 00000040 00000000 00000040 RWIX
ECAP3 00005280 00000040 00000000 00000040 RWIX
ECAP4 000052c0 00000040 00000000 00000040 RWIX
ECAP5 00005300 00000040 00000000 00000040 RWIX
ECAP6 00005340 00000040 00000000 00000040 RWIX
ECAP7 00005380 00000040 00000000 00000040 RWIX
PGA1 00005b00 00000010 00000000 00000010 RWIX
PGA2 00005b10 00000010 00000000 00000010 RWIX
PGA3 00005b20 00000010 00000000 00000010 RWIX
PGA4 00005b30 00000010 00000000 00000010 RWIX
PGA5 00005b40 00000010 00000000 00000010 RWIX
PGA6 00005b50 00000010 00000000 00000010 RWIX
PGA7 00005b60 00000010 00000000 00000010 RWIX
DACA 00005c00 00000010 00000000 00000010 RWIX
DACB 00005c10 00000010 00000000 00000010 RWIX
CMPSS1 00005c80 00000020 00000000 00000020 RWIX
CMPSS2 00005ca0 00000020 00000000 00000020 RWIX
CMPSS3 00005cc0 00000020 00000000 00000020 RWIX
CMPSS4 00005ce0 00000020 00000000 00000020 RWIX
CMPSS5 00005d00 00000020 00000000 00000020 RWIX
CMPSS6 00005d20 00000020 00000000 00000020 RWIX
CMPSS7 00005d40 00000020 00000000 00000020 RWIX
SDFM1 00005e00 00000080 00000000 00000080 RWIX
SPIA 00006100 00000010 00000000 00000010 RWIX
SPIB 00006110 00000010 00000000 00000010 RWIX
CLAPROMCRC 000061c0 00000020 00000000 00000020 RWIX
PMBUSA 00006400 00000020 00000000 00000020 RWIX
FSITXA 00006600 00000080 00000000 00000080 RWIX
FSIRXA 00006680 00000080 00000000 00000080 RWIX
LINA 00006a00 00000100 00000000 00000100 RWIX
LINB 00006b00 00000100 00000000 00000100 RWIX
WD 00007000 00000040 00000000 00000040 RWIX
NMIINTRUPT 00007060 00000010 00000000 00000010 RWIX
XINT 00007070 00000010 00000000 00000010 RWIX
SCIA 00007200 00000010 00000000 00000010 RWIX
SCIB 00007210 00000010 00000000 00000010 RWIX
I2CA 00007300 00000040 00000000 00000040 RWIX
ADCA 00007400 00000080 00000000 00000080 RWIX
ADCB 00007480 00000080 00000000 00000080 RWIX
ADCC 00007500 00000080 00000000 00000080 RWIX
INPUT_XBAR 00007900 00000020 00000000 00000020 RWIX
XBAR 00007920 00000020 00000000 00000020 RWIX
SYNC_SOC 00007940 00000010 00000000 00000010 RWIX
DMACLASRCSEL 00007980 00000040 00000000 00000040 RWIX
EPWM_XBAR 00007a00 00000040 00000000 00000040 RWIX
CLB_XBAR 00007a40 00000040 00000000 00000040 RWIX
OUTPUT_XBAR 00007a80 00000040 00000000 00000040 RWIX
GPIOCTRL 00007c00 00000200 00000000 00000200 RWIX
GPIODAT 00007f00 00000040 00000000 00000040 RWIX
RAMLS5 0000a800 00000800 0000035a 000004a6 RWIX
RAMLS6 0000b000 00000800 0000078f 00000071 RWIX
RAMLS7 0000b800 00000800 00000346 000004ba RWIX
RAMGS0 0000c000 00002000 00000000 00002000 RWIX
RAMGS1 0000e000 00002000 00000000 00002000 RWIX
RAMGS2 00010000 00002000 00000000 00002000 RWIX
RAMGS3 00012000 00001ff8 00000000 00001ff8 RWIX
CANA 00048000 00000800 00000000 00000800 RWIX
CANB 0004a000 00000800 00000000 00000800 RWIX
DEV_CFG 0005d000 00000180 00000000 00000180 RWIX
CLK_CFG 0005d200 00000100 00000000 00000100 RWIX
CPU_SYS 0005d300 00000100 00000000 00000100 RWIX
PERIPH_AC 0005d500 00000200 00000000 00000200 RWIX
ANALOG_SUBSYS 0005d700 00000100 00000000 00000100 RWIX
DCC0 0005e700 00000040 00000000 00000040 RWIX
ERAD_GLOBAL 0005e800 00000013 00000000 00000013 RWIX
ERAD_HWBP1 0005e900 00000008 00000000 00000008 RWIX
ERAD_HWBP2 0005e908 00000008 00000000 00000008 RWIX
ERAD_HWBP3 0005e910 00000008 00000000 00000008 RWIX
ERAD_HWBP4 0005e918 00000008 00000000 00000008 RWIX
ERAD_HWBP5 0005e920 00000008 00000000 00000008 RWIX
ERAD_HWBP6 0005e928 00000008 00000000 00000008 RWIX
ERAD_HWBP7 0005e930 00000008 00000000 00000008 RWIX
ERAD_HWBP8 0005e938 00000008 00000000 00000008 RWIX
ERAD_CTR1 0005e980 00000010 00000000 00000010 RWIX
ERAD_CTR2 0005e990 00000010 00000000 00000010 RWIX
ERAD_CTR3 0005e9a0 00000010 00000000 00000010 RWIX
ERAD_CTR4 0005e9b0 00000010 00000000 00000010 RWIX
DCSM_BANK0_Z1 0005f000 00000030 00000000 00000030 RWIX
DCSM_BANK0_Z2 0005f040 00000030 00000000 00000030 RWIX
DCSM_COMMON 0005f070 00000010 00000000 00000010 RWIX
DCSM_BANK1_Z1 0005f100 00000030 00000000 00000030 RWIX
DCSM_BANK1_Z2 0005f140 00000030 00000000 00000030 RWIX
MEMCFG 0005f400 00000080 00000000 00000080 RWIX
ACCESSPROTECTION 0005f4c0 00000040 00000000 00000040 RWIX
MEMORYERROR 0005f500 00000040 00000000 00000040 RWIX
FLASH0_CTRL 0005f800 00000300 00000000 00000300 RWIX
FLASH0_ECC 0005fb00 00000040 00000000 00000040 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
codestart
* 0 00082000 00000002
00082000 00000002 f28004x_codestartbranch.obj (codestart)
.cinit 0 000844d4 0000023c
000844d4 000000cb (.cinit..data.1.load) [load image, compression = lzss]
0008459f 0000005d (.cinit..data.2.load) [load image, compression = lzss]
000845fc 00000042 (.cinit..data.3.load) [load image, compression = lzss]
0008463e 00000035 (.cinit.controlVariables.load) [load image, compression = lzss]
00084673 0000002c (.cinit..data.4.load) [load image, compression = lzss]
0008469f 00000029 (.cinit..data.5.load) [load image, compression = lzss]
000846c8 00000006 (__TI_handler_table)
000846ce 00000004 (.cinit..boot_data_sec.load) [load image, compression = zero_init]
000846d2 00000004 (.cinit..bss.load) [load image, compression = zero_init]
000846d6 00000004 (.cinit..scratchpad.load) [load image, compression = zero_init]
000846da 00000004 (.cinit.Cla1ToCpuMsgRAM.load) [load image, compression = zero_init]
000846de 00000004 (.cinit.CpuToCla1MsgRAM.load) [load image, compression = zero_init]
000846e2 00000002 --HOLE-- [fill = ffff]
000846e4 0000002c (__TI_cinit_table)
.stack 1 00000400 000003f8 UNINITIALIZED
00000400 000003f8 --HOLE--
.init_array
* 0 00084000 00000000 UNINITIALIZED
Bootloader Map
******************************************************************************
TMS320C2000 Linker PC v21.6.0
******************************************************************************
>> Linked Wed Feb 15 10:04:48 2023
OUTPUT FILE NAME: <bootloader.out>
ENTRY POINT SYMBOL: "code_start" address: 00080000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
RAMM0 00000008 000003f8 000003f8 00000000 RWIX
RAMLS0 00008000 00000800 00000000 00000800 RWIX
RAMLS1 00008800 00000800 00000000 00000800 RWIX
RAMLS34 00009800 00001000 00000a59 000005a7 RWIX
BEGIN 00080000 00000002 00000002 00000000 RWIX
FLASH_BOOT 00080002 00001ffe 00001553 00000aab RWIX
FLASH_BANK0_SEC2 00082000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC3 00083000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC4 00084000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC5 00085000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC6 00086000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC7 00087000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC8 00088000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC9 00089000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC10 0008a000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC11 0008b000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC12 0008c000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC13 0008d000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC14 0008e000 00001000 00000000 00001000 RWIX
FLASH_BANK0_SEC15 0008f000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC0 00090000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC1 00091000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC2 00092000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC3 00093000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC4 00094000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC5 00095000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC6 00096000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC7 00097000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC8 00098000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC9 00099000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC10 0009a000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC11 0009b000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC12 0009c000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC13 0009d000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC14 0009e000 00001000 00000000 00001000 RWIX
FLASH_BANK1_SEC15 0009f000 00000ff0 00000000 00000ff0 RWIX
RESET 003fffc0 00000002 00000000 00000002 RWIX
PAGE 1:
BOOT_RSVD 00000002 000000f1 00000001 000000f0 RWIX
RAMM1 00000400 000003f8 00000000 000003f8 RWIX
RAMLS2 00009000 00000800 00000000 00000800 RWIX
RAMLS5 0000a800 00000800 00000000 00000800 RWIX
RAMLS6 0000b000 00000800 00000000 00000800 RWIX
RAMLS7 0000b800 00000800 00000000 00000800 RWIX
RAMGS0 0000c000 00002000 00000000 00002000 RWIX
RAMGS1 0000e000 00002000 00000000 00002000 RWIX
RAMGS2 00010000 00002000 00000000 00002000 RWIX
RAMGS3 00012000 00001ff8 00000000 00001ff8 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.stack 0 00000008 000003f8 UNINITIALIZED
00000008 000003f8 --HOLE--
codestart
* 0 00080000 00000002
00080000 00000002 f28004x_codestartbranch.obj (codestart)
.cinit 0 00081530 0000002c
00081530 0000000f (.cinit..data.load) [load image, compression = lzss]
0008153f 00000001 --HOLE-- [fill = ffff]
00081540 00000006 (__TI_handler_table)
00081546 00000004 (.cinit..boot_data_sec.load) [load image, compression = zero_init]
0008154a 00000004 (.cinit..bss.load) [load image, compression = zero_init]
0008154e 00000002 --HOLE-- [fill = ffff]
00081550 0000000c (__TI_cinit_table)
.init_array
* 0 00080004 00000000 UNINITIALIZED
.bss 0 0000a1d8 0000006e UNINITIALIZED
0000a1d8 00000040 cfp_svcMngr.obj (.bss:service_table)
0000a218 00000020 sfa_update_manager.obj (.bss:buf)
0000a238 00000006 cfp_bls_tms32_f28004x.obj (.bss)
0000a23e 00000001 cfp_critical_section_f28004x.obj (.bss)
0000a23f 00000001 --HOLE--
0000a240 00000006 cfp_svcMngr.obj (.bss)
.const 0 000813a8 00000186
000813a8 0000009b driverlib_eabi.lib : flash.obj (.const:.string)
00081443 00000001 --HOLE-- [fill = ffff]
00081444 0000009a : sysctl.obj (.const:.string)
000814de 00000050 : cputimer.obj (.const:.string)
.reset 0 003fffc0 00000000 DSECT
Hello Jan,
One of our compiler tools experts will respond to this question shortly.
Thanks,
Ibukun
Hello Jan,
For a little more background, could you share exactly how you are branching from your bootloader program to your application?
Best regards,
Ibukun
Hi Ibukun,
I already resolve the problem sorry for late notice.
the problem is in the f28004x_codestartbranch.asm, i am directly calling the main function instead of _c_int00 which will execute the .cinit. please see code below.
***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
.if WD_DISABLE == 1
.text
wd_disable:
SETC OBJMODE ;Set OBJMODE for 28x object code
EALLOW ;Enable EALLOW protected register access
MOVZ DP, #7029h>>6 ;Set data page for WDCR register
MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD
EDIS ;Disable EALLOW protected register access
;LB _c_int00 ;Branch to start of boot._asm in RTS library
LCR main
; Cleanup and exit. At this point the EntryAddr
; is located in the ACC register
LB ExitBoot
.endif
;end wd_disable
I reverted it back to "LB _c_int00"
then I change the implementation of jump from bootloader to application through the code below.
For jump in application:
asm(" LB 0x082000 ")
For jump in bootloader:
asm(" LB 0x080000 ")
This code works and able to execute .cinit as well.
Thank you for your response in my question.
I will mark this as resolved.
Best Regards,
Jan
