TMS320F280039C: 39C SPI Mater receive interrupt issue

Rahul,

Based on your SPIA configuration, your SPIA should get interrupt when you receive 1 byte (SPI_FIFO_RX1). I would also encourage you to use SPI_setEmulationMode(SPIA_MASTER_BASE, SPI_EMULATION_FREE_RUN); instead of SPI_setEmulationMode(SPIA_MASTER_BASE, SPI_EMULATION_STOP_AFTER_TRANSMIT);

Did you enter ISR (INT_SPIA_MASTER_RX_ISR)? If so, it looks like SPIA did interrupt CPU (this means you did receive 1 byte).

Recommended example: spi_ex4_external_loopback_fifo_interrupts.c (C2000Ware)

Regards,

Manoj

Hi Manoj,

GPIO0 is configured as GPIO_0_SPIB_STE ( chip select) . do i need to keep STE pin low by softwere to select slave or hardware will take care. you can see my above example code where i disabled CS pin .

Hi Manoj ,

my 2nd query is i want to configure SPIA as master with one byte receive  FIFO interrupt  (Tx FIFO interrupt not required). 

please check my configuration. 

i am facing issue. after master transmit immediately getting receive FIFO interrupt but slave is not connected . Check below snap.

i am Master is  transmitting 0xBD but  immediately getting RXFIFO interrupt where i am receiving 0xBD00 . see in above snap.

my configuration: 

please let me know what is the issue .

rData updatedin RXFIFO interrupt. (0xBDFF)

Hi manoj ,

i entered in MASTER Rx ISR but slave is not connected.

It is my understanding that you have two boards. Board1. SPIA acting as master and board2. SPIA acting as slave. Are these board connected by connecting SPI signals?

yes , but board 2  which is slave not sending any data to master(board1) but master getting receive interrupt. 

Did you try have the slave SPI ready with the data that needs to be transmitted then you shouldn't have this problem.

Regards,

Manoj

Hi Manoj ,

SPI slave is not connected yet to master. i am just transmitting 1 byte through master but Master RXFIFO interrupt is getting trigger.

please check below snap.

Why i am getting SPIRXBUF = 0x00FF ? 

here is my configuration : 

void SPIA_Master_init(){
SPI_disableModule(SPIA_Master_BASE);
SPI_setConfig(SPIA_Master_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0,
SPI_MODE_MASTER, 500000, 8);
SPI_enableFIFO(SPIA_Master_BASE);
SPI_setFIFOInterruptLevel(SPIA_Master_BASE, SPI_FIFO_TXEMPTY, SPI_FIFO_RX1);
SPI_clearInterruptStatus(SPIA_Master_BASE, SPI_INT_RXFF);
SPI_enableInterrupt(SPIA_Master_BASE, SPI_INT_RXFF);
SPI_disableLoopback(SPIA_Master_BASE);
SPI_setEmulationMode(SPIA_Master_BASE, SPI_EMULATION_FREE_RUN);
SPI_enableModule(SPIA_Master_BASE);
}

Rahul,

There is miscommunication and I'm getting conflicting information from you. Is SPI (slave) connected to master? Below message says so.

But, then in the next thread, you say SPI slave is not connected. which is true?

According to SPI protocol, whenever SPI master transmits any data on SPIMOSI pin, it will parallely strobe for data on SPISOMI pin. If the SPISOMI pin is low, it will pick it as valid data and say it received 0xFF. It doesn't matter if SPI slave is connected (or) not. what matters is the state of SPISOMI pin.

Regards,

Manoj

Slave is not sending data means it is not connected. 

Hi Manoj ,

what should be the default state of MISO in case slave is not connected so Master should not receive garbage to enter in Rx fifo isr?

If you have pull-up enabled on MISO pin, then you would read 0xFF as received byte.

Hi Manoj ,

My requirement is SPI Master should transmit one byte data & receive one byte data through FIFO interrupt ( only if slave transmit data).

Rahul,

Did you try have the slave SPI ready with the data that needs to be transmitted before SPI master initiates 1 byte transaction?

Regards,

Manoj