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TMS320F28377D: External clock disturbances

Mike Twieg1
Intellectual 390 points
Part Number: TMS320F28377D


Hello,

In my application my F28377D MCU must be frequency locked to one of two 10MHz external clock sources. An external logic circuit selects which clock is multiplexed to the MCU's XCLKIN (pin X1). In normal operation, XCLKIN is used as the reference to the internal PLL, which produces a 200MHz sysclk for the MCU.

The two 10MHz clock sources are not exactly frequency or phase locked. My concern is what may happen to the MCU during the switchover between the two. Depending on the timings, I may see a phase jump, and possibly a runt pulse. I doubt this will trigger a CLOCKFAIL via the MCD logic, but I'm worried that the output of the PLL may be disturbed in a way that causes erroneous operation of the CPU or peripherals.

It's also possible that the external clock source currently in use will fail. In this case, the external logic circuit should detect the missing clock and switch to the other 10MHz source within 100us. But is there a risk that during that time the PLL frequency may drift high enough to caus erroneous operation of the CPU or peripherals? If I enable the PLL slip ISR, can I assume that ISR will fire before the PLL drifts too much?

Regards,

Mike

  • 0
    TI__Prodigy 470 points

    Hi,

    The expert is out of the office because of Holiday. Please expect a reply by Tuesday.

    Thanks.

  • 0
    TI__Guru* 95315 points

    Mike,

             I presume you have two external 10 MHz clock sources so that you can switch to the other in case the current one fails. IOW, the “switchover” would be warranted only when the current clock source fails. i.e. the switchover is not a deterministic event, correct?

    Mike Twieg1 said:
    Depending on the timings, I may see a phase jump, and possibly a runt pulse.

    True.

    Mike Twieg1 said:
    I doubt this will trigger a CLOCKFAIL via the MCD logic,

    The MCD logic is counter-based. So, if the external switchover is "fast enough", MCD will not be triggered.

    Mike Twieg1 said:
    I'm worried that the output of the PLL may be disturbed in a way that causes erroneous operation of the CPU or peripherals.

    It is possible. The input-clock is the heartbeat to which every operation is synchronized. so, any disturbance to the input clock, even a transient disturbance, will have an impact.

    Mike Twieg1 said:
    But is there a risk that during that time the PLL frequency may drift high enough to caus erroneous operation of the CPU or peripherals?

    If there is a loss of i/p clock, I don't see a risk of too high a frequency from the PLL. Perhaps I am missing something?

    Mike Twieg1 said:
    If I enable the PLL slip ISR, can I assume that ISR will fire before the PLL drifts too much?

    I presume you will use a GPIO pin in the PLLSLIP ISR to switch the external clock source?