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TMS320F28075: How to use McBSP in SPI mode (Clock Stop Mode) and operate it by external clock input

O.H
Mastermind 7290 points

Part Number: TMS320F28075
Other Parts Discussed in Thread: MSP430FR5959, MSP430FR5969

Hi experts,

I am trying to use McBSP in SPI mode (Clock Stop Mode) and operate it by external clock input. I want to connect an external crystal oscillator (1MHz) to generate 19200bps.
Please tell me about the following.

When using McBSP in SPI mode, is it possible to use anything other than "LSPCLK"?
Is it possible to achieve the above by inputting an external clock to MCLKXB?

If possible, I would like to avoid using LSPCLK because it requires lowering the CPU operating frequency. As described in TRM "20.7.2 Clock Stop Mode," we believe that in the SPI mode (Clock Stop Mode) of McBSP, the receive clock signal (MCLKR) cannot be used because it is internally connected to the transmit clock signal (CLKX).

Best regards,
O.H

  • 0
    TI__Guru* 86290 points

    O.H.

    Your understanding is correct.  However, while the system derived clock to the McBSP from the system is LSPCLK, the final clock frequency used by the McBSP is from the clock generator, which has an additional divider CLKGDV; this clock rate is defined as below. 

    So you should be able to divide down LSPCLK further in the McBSP as needed.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Mastermind 7290 points

    Hi Matthew,

    Thank you for your support.

    MatthewPate said:

    Your understanding is correct.  However, while the system derived clock to the McBSP from the system is LSPCLK, the final clock frequency used by the McBSP is from the clock generator, which has an additional divider CLKGDV; this clock rate is defined as below. 

    So you should be able to divide down LSPCLK further in the McBSP as needed.

    I believe that 19200bps can be achieved by combining "CLKGDV" and "LSP Divider" when using LSPCLK as a reference. However, I think I need to drop CPUCLK(SYSCLK) to about 34MHz. (34.406.400/14/128=19200)

    Therefore, we will use an external clock input to MCLKXB.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru* 86290 points

    O.H.

    CLKGDV is 8 bit field, so it should give 1 - 256 divide options, but as you said this is still too big to get 19200bps from the 120MHz max CPU clock on this device.  You'd need to drop the CPU clock in the 50-60MHz range to get the dividers to work out.

     In order to preserve the SYSCLK would it make sense to just bit bang the SPI data on a GPIO to get the target datarate?

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Mastermind 7290 points

    Hi Matthew,

    Thank you for your advice.

    The customer confirmed the operation of McBSP-B with the following settings, but it did not work well.

    I read again TRM "20.7.6 McBSP as the SPI Master", and it says "For SPI master operation, the MCLKX pin must be configured as an output.". Therefore, it appears that when using SPI mode, it only works with LSPCLK.

    If there is anything missing in the following settings, could you please point it out?

    • GPIO24 -> MDXB: McBSP-B data transmission
    • GPIO25 -> MDRB: McBSP-B data reception
    • GPIO26: MCLKXB: Clock output from McBSP-B
      • Input/output direction register: Output setting
    • GPIO86→MCLKXB: External reference clock input (1MHz supplied externally)
      • Input/output direction register: input setting
    • Clock setting: CLKSM=1, SCLKSME=1, divide by 52 (19230bps)
    MatthewPate said:
    In order to preserve the SYSCLK would it make sense to just bit bang the SPI data on a GPIO to get the target datarate?

    If only LSPCLK is available, we have no choice but to use the method you suggest.

    I found the following thread and sample code. If you have better information for C2000, could you please let me know?

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru* 86290 points

    O.H.,

    Please give me an additional day to respond.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Guru* 86290 points

    O.H.

    We don't have any direct examples for C2000, those you have provided will be good from a theoretical standpoint to use C2000 HW to implement.  One thing to keep in mind is that C28x does not support byte access so you will need to keep that in mind when adopting most SPI codes from byte addressable machines.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Mastermind 7290 points

    Hi Matthew,

    MatthewPate said:
    We don't have any direct examples for C2000, those you have provided will be good from a theoretical standpoint to use C2000 HW to implement.  One thing to keep in mind is that C28x does not support byte access so you will need to keep that in mind when adopting most SPI codes from byte addressable machines.

    Thank you for your reply. We note the above.

    Could you give me your views on the following? When using McBSP in SPI mode, is it not possible to approach to input a reference clock to MCLKXB?

    O.H said:

    The customer confirmed the operation of McBSP-B with the following settings, but it did not work well.

    I read again TRM "20.7.6 McBSP as the SPI Master", and it says "For SPI master operation, the MCLKX pin must be configured as an output.". Therefore, it appears that when using SPI mode, it only works with LSPCLK.

    If there is anything missing in the following settings, could you please point it out?

    • GPIO24 -> MDXB: McBSP-B data transmission
    • GPIO25 -> MDRB: McBSP-B data reception
    • GPIO26: MCLKXB: Clock output from McBSP-B
      • Input/output direction register: Output setting
    • GPIO86→MCLKXB: External reference clock input (1MHz supplied externally)
      • Input/output direction register: input setting
    • Clock setting: CLKSM=1, SCLKSME=1, divide by 52 (19230bps)

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Guru* 86290 points

    Since both GPIO26 and GPIO86 are MCLKX, I believe that this is an illegal selection to have same signal from multiple GPIOs.  I think C28x will pick lowest GPIO number in this case, i.e. outputting clock on GPIO26.

    Even though TRM mentions that CLKX is always output, it also mentions that CLKX and CLKR are internally tied together.  Can customer try the same settings for the clock registers, but instead of supplying 1MHz on MCLKXB configure the appropriate GPIO as MCLKRB and input 1MHz clock on that pin to see if this works?

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Mastermind 7290 points

    Hi Matthew,

    Thank you for your reply. I understood.

    MatthewPate said:
    Even though TRM mentions that CLKX is always output, it also mentions that CLKX and CLKR are internally tied together.  Can customer try the same settings for the clock registers, but instead of supplying 1MHz on MCLKXB configure the appropriate GPIO as MCLKRB and input 1MHz clock on that pin to see if this works?

    Sorry for the lack of explanation. Initially we used MCLKRB(GPIO60). We had checked with the same setup but it did not work...

    Best regards,
    O.H

  • +1 in reply to O.H
    TI__Guru* 86290 points

    O.H.

    Thanks for the clarification, based on these experiments along with the note in the DS, I agree in SPI Clock Stop mode the clock must come from LSPCLK only.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Mastermind 7290 points

    Hi Matthew,

    I understood. Thank you for your support.

    Best regards,
    O.H