TMS320F28388D: EtherCAT: Latch0 timestamp as reference for the system time

Additional question: Does the IP ESC Register 0x910 behave as described in the Register description of the Beckhoff ET1100 ?
From ET1100 register description: "Write access: Written value will be compared with Latch0 Time Positive Edge time. The result is an input to the time control loop."

Hi Tomas,

The ESC in F2838x is very similar to ET1100. You can reference Beckhoff's datasheet for registers: https://download.beckhoff.com/download/document/io/ethercat-development-products/ethercat_esc_datasheet_sec2_registers_2i9.pdf

Tomas Kropaci said:

Additional question: Does the IP ESC Register 0x910 behave as described in the Register description of the Beckhoff ET1100 ?

Yes, it should. There is a function, GetSystemTimeDelay(), which accesses the System Time registers (0x910:0x913) in 'ecatappl.c' file of our C2000WARE projects. You can reference this.

Best,

Kevin

Thank you very much for your response !
I know the ET1100 and it's data sheets. I try to create a DC Master Clock which is syncronized to a external clock.
This external clock is connected to the EtherCAT slave which I will configure to be the Master Clock.
The special write functionality of Register 0x910 is crucial.

Does the ESC IP Register 0x910 write access behave as described in ET1000 data sheet section 2 ?

In order to understand my scenario please see  ET1100 data sheet section 1 \ Distributed Clock \ System Time PDI Controlled

Thank you very much for your support !
Kind regards, Tomas