I followed the labs so far which I found under F2806x Workshop (ti.com)
I appreciate the help from these guides as they give me a good/ genereal understanding of different modules.
Currently, I am working on Lab 7 where there are a couple of Questions in the end:
How do the captured values for PwmDuty and PwmPeriod relate to the compare register CMPA and time-base period TBPRD settings for ePWM1A?
• What is the value of PwmDuty in memory?
• What is the value of PwmPeriod in memory?
• How does it compare with the expected value?
My answers are:
PwmDuty: 4294951119
PwmPeriod: 4294951119
exptected value: From CMPA I would have expected a value of CMPA = 75% ∗TBPRD=0.75 ∗TBPRD=16875
where TBPRD is TBPRD=1/2∗ 90MHz/2kHz=22500
In my debug session within the ISR for ECAP1_INT:
CAP1 has a value of 4294951119
while CAP2 and CAP3 remain 0
the respective ISR is given as
interrupt void ECAP1_INT_ISR(void) // PIE4.1 @ 0x000D70 ECAP1_INT
{
PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; // Must acknowledge the PIE group
ECap1Regs.ECCLR.bit.INT = 1; // Clear the ECAP1 interrupt flag
ECap1Regs.ECCLR.bit.CEVT3 = 1; // Clear the CEVT3 flag
// Compute the PWM duty period (rising edge to falling edge)
PwmDuty = (int32)ECap1Regs.CAP2 - (int32)ECap1Regs.CAP1;
// Compute the PWM period (rising edge to rising edge)
PwmPeriod = (int32)ECap1Regs.CAP3 - (int32)ECap1Regs.CAP1;
}
I adapted the registry entries as given in the solution for ECAP_7_8_9_10_12.c:
ECap1Regs.ECCTL2.all = 0x0096; // ECAP control register 2 // bit 15-11 00000: reserved // bit 10 0: APWMPOL donot care // bit 9 0: CAP/APWM, select Capture mode instead of APWM mode // bit 8 0: SWSYNC donot care // bit 7-6 10: SYNCO_SEL Sync-Out Select disabled, i.e. 1x // bit 5 0: SYNCI_EN (sync disbale) // bit 4 1: TSCTRSTOP timer stamp counter run // bit 3 0: RE-ARM rearm disable // bit 2-1 11: STOP_WRAP wrap capture after capture event 4 // bit 0 0: CONT/ONESHT continuous mode ECap1Regs.ECCTL1.all = 0xC144; // ECAP control register 1 // bit 15-14 11: FREE/SOFT, 11 = ignore emulation suspend // bit 13-9 00000: PRESCALE divide by 1 // bit 8 1: CAPLDEN CAP1-4: Load on Capture Event - enable // bit 7 0: CTRRST4 donot care // bit 6 1: CAP4POL trigger on falling (1) edge // bit 5 0: CTRRST3 // bit 4 0: CAP3POL trigger on rising (0) edge // bit 3 0: CTRRST2 // bit 2 1: CAP2POL trigger on falling (1) edge // bit 1 0: CTRRST1 // bit 0 0: CAP1POL trigger on rising (0) edge ECap1Regs.ECEINT.all = 0x0002; // Enable desired eCAP interrupts // bit 15-8 0's: reserved // bit 7 0: CTR=CMP donot care // bit 6 0: CTR=PRD donot care // bit 5 0: CTROVF donot care // bit 4 0: CEVT4 disable // bit 3 0: CEVT3 disable // bit 2 0: CEVT2 disable // bit 1 1: CEVT1 enable // bit 0 0: reserved PieCtrlRegs.PIEIER4.bit.INTx1 =1; // Enable ECAP1_INT in PIE group 4 IER |= 0x0008;
The only difference in comparison to the solution is in ECEINT. The solution suggests 0x0008 while I chose 0x0002. Somehow, if using the suggestion of the solution, there is no interrupt.
Two questions arise:
Why are CAP2 and CAP3 values 0 ?
Why can I not use the the other events? The number here indicates after how many number of events an interrupt should trigger if I understood this correctly?
