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TMS320F28384S: CM-UART problems

Part Number: TMS320F28384S


Hello, 

I am developing a very simple application where the CM-UART waits to receive a character at a time which is immediately retransmitted back.

I have configured CM-UART at 9600 8N1, no FIFO.

Then I send a character with PuTTY, and the CM-UART interrupt handler is triggered as expected.

However, when I try to read the received character, the UART_readCharacter() function loops indefinitely, waiting for RXFE bit to be set in the UARTFR register.

The problem is that RXFE bit is set and the caracter is available in the UARTDR register, as you can see from the image below.

What I am doing wrong?

Thank you,

Carlo

  • Moreover, when a character is received and the ISR is triggered, no RXRIS / RXMIS is set in the UARTRIS / UARTMIS register.

    Thank you,

    Carlo.

  • Hi Carlo,

    Thanks for your question. Are you using FIFO? If not, then the functionality of the RXFE bit changes, see below from the TRM register field. This change of functionality could be the culprit if you're expecting FIFO content vs receive holding register:

    Regards,

    Vince

  • Thank you Vince,

    yes to make things simpler I have disabled FIFO.

    So, if FIFO are disabled, it seems that I cannot use any of the reading APIs (UART_isDataAvailable(), UART_readCharNonBlocking(), UART_readChar()), either any of the writing APIs (UART_isSpaceAvailable(), UART_writeChar()).
    The first ones, indeed, check RXFE flag status, that is always at 1 if FIFO is disabled (empty RXFIFO), while the second ones check TXFF flag status, that is always at 1 if FIFO is disabled (full TXFIFO).

    If so, not having a driverlib_cm support, nor the cm bitfield registers support, the only solution seems to define a cup of macros, based on HW_REG() to access directly the data register UARTDR.

    #define UART_ReadCharNonFIFO() (HWREG(UART0_BASE + UART_O_DR))
    #define UART_WriteCharNonFIFO(c) (HWREG(UART0_BASE + UART_O_DR) = c)

    Is it right?

    Another strange think that I have noticed, is that each time the UART interrupt handler is triggered, the interrupt status returned from UART_getInterruptStatus() is correct: 0x010 in case of reception, 0x020 in case of trasmission.
    Any way, in case of reception, if I read the UARTRIS/UARTMIS registers in the watch window, the RXRIS/RXMIS flags are set to 0, even before calling UART_clearInterruptStatus() or reading the received character.
    No problems on transmission, instead.

    Which can be the reason?

    Thank you,
    Carlo

  • Hi Carlo,


    Can you confirm that the data is actually being received at the pin? This could be a pin configuration issue (where the RX pin Gpio Mux settings may not be set properly).

    A scope capture of the RX may provide some help here.

    Regards,

    Vince

  • Hello Vince,
    after having defined UART_ReadCharNonFIFO() and UART_WriteCharNonFIFO(c) macros, as said in my previous post, I receive and retransmit characters correctly. So it can't be a pin mux issue.

    The image below, refers to a character reception event.
    The UART interrupt handler is triggered correctly, the UART_getInterruptStatus() returns 0x010 correctly, but RXRIS / RXMIS flags in the watch wondows are at 0.

    Thank you,
    Carlo

  • Hi Carlo,

    Thanks for the clarification! So this is intended behavior then, if you are referring to the UARTRIS.RXRIS bit. That bit gets cleared when either the FIFO is read (for FIFO mode) or when a single byte is read (for non-FIFO mode). In this case, the custom ReadChar function you created will read the byte and clear the RXRIS bit at the same time.

    Regards,

    Vince

  • Hello Vince,

    the problem is that I haven't read the character yet.
    I was stopped on a breakpoint just after calling the UART_getInterruptStatus() to get the interrupt reason.

    I have also noticed that the problem occours even if a stop before executing the UART_getInterruptStatus(). In this case the UART_getInterruptStatus() fails too, and returns 0.

    Thank you,

    Carlo

  • Hi Carlo,

    Does this only happen when you're running with breakpoints? If it's only with breakpoints, then likely the break is occurring mid-transmission and interrupting the clocking of the received data. Can you do a free-run without breakpoints and see if that fixes it?

    Regards,

    Vince

  • Hi Vince,

    yes I confirm that I have no problems when running in free run.

    So it seems to be a debugger problem, isn't it? 

  • Hi Carlo,

      

    Correct, this appears to be an issue with how the debugger interrupts the SCI module. You can theoretically use the SCIRXEMU register for modifying how SCI reacts to breakpoints. Let me know if that works for this particular issue. If not, I can contact the debugger expert, they may be able to assist with this question.

      

    Regards,

    Vince

  • Hi Vince, 

    SCIRXEMU is a C28 SCI peripheral register and not a CM UART one.

    I can't find a similar register for CM UART.

    Anyaway, perhaps that the reason of this problem could be that  RXRIS / RXMIS flags are cleared because the rx data register is read by emulator to update the watch window.

    I don't know... Anyway it seems to be a debugger issue and not an hw/sw problem.

    Thank you,

    Carlo.

  • Hi Carlo,

    I will contact our debugger expert and have them reply on this, please allow for 1-2 business days for reply.

    Regards,

    Vince

  • Hi Carlo,

    You are correct that the debugger is the reason for this, in normal operation, the clocks to the UART output do not get stopped (there is no clock stop in normal system operation, only in breakpoints).

    Regards,

    Vince