Customer asking about HWBIST procedures executed in boot ROM.
After CPU reset from CCS debugger, or power cycle on/off the CPU2 doesn’t boot correctly – here are recent observation (screenshots are form spruhm8i – 2837XD TRM) :
- After resetting CPU1 from the debugger, the CPU2 is also reset, and then it enters infinite wait - CPU1 stops at some point, but after clicking "run" it boots correctly.
- Then, After clicking "restart", which is jump to "codestart", on CPU2 it runs correctly. So assuming there is some problem with the boot ROM.
- They checked the Boot ROM status registers:
CPU1 Boot ROM Status - address 0x2C: 0x0F00 which means the following errors:
CPU1 Boot Mode Status - address 0x38: 0x0B - Flash Boot - that's fine
CPU2 Boot ROM Status - adrress 0x02: 0x0D00
which means the following errors:
CPU1 after reset stops in Boot 0x3FE44F, but after clicking run it continues.
CPU2 waits in 0x3FE44F - Idle Mode Wait Point
This is expected behavior for HWBIST error:
Summarizing, they have HWBIST error after reset, and that's why their CPUs work like that. Another question is why does this happen?
Does this mean that we have some hardware faults? This happens on all three boards that they currently have for testing.
They have also tried reset using TI provided example located in [C2000 ware location]\driverlib\f2837xd\examples\dual\led
Any information about how the HWBIST procedure at run-time works and what can cause this error? Unfortunately I was unable to find any resource on that.
