TMS320F28386D: TMS320F28386D

(I thought i shall  increase one by one PLLSYSCLK)

Hello W,

Could you explain the details of the "test" you are referring to above?

Thanks,
Ibukun

The test means watch low 32-bit of the free 64-bit free-running counter, like the below picture shows.

The PLL Clock is 200Mhz.  It means each PLL cycle shall take 5ns（1/200MHz）

unsigned 32 bit integer 0 ~ 4294967295, so the low 32 bit of 64-bit counter shall counter almost 20s maximum(4294967295*5ns)，if the counter increase one by one PLLSYSCLK. But in the test result it shows almost 40s.  

It proves that  the counter increase one by two PLLSYSCLK(10ns)

I must confirm this information. Due to I need use this timestamp to do  data transmission delay measurement between CPU2 and CM core.

Can you confirm the value of CLKCFGREGS.SYSCLKDIVSEL?

Hi W Z,

Ibukun will be out of office until next week. I will assign this thread to our IPC expert to answer  your latest question.

WZ,

As Ibukun mentioned, IPCCOUNTER register is clocked by PLLSYSCLK. If you timing is off, we need to check your PLL configuration register. I'm wondering whether you are clocking @ 100 MHz instead of 200 MHz. Please share your PLL configuration registers.

The snapshot you had sent is for CLKCFGLOCK1 register. We don't need to this. We need to ClkCfgRegs registers.

Regards,

Manoj

Thanks for the recommend to use the ClockTree tool. I will try it later.

But let's back to the orignal question.

The  64-bit free-running counter increase one by x PLLSYSCLK.

How much is the value of x?