Part Number: TMS320F28035
Other Parts Discussed in Thread: TMS320F28335
How to configure F28035 CAN to receive all the messages?
Below, InitCAN function I'm using.
Still not working except the ID set on MAILBOX.
Means, it receives one ID per mailbox!!
I am using various other controllers, but never found this limitation.
So, can anybody help me to configure to receive all IDs please?
Thanks in advance
Sandeep
//--------------------------------------------------------------------------------------------------------------------------------------------------
void InitECAN(void)
{
struct ECAN_REGS ECanaShadow;
EALLOW; // EALLOW enables access to protected bits
/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
/* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
See Note at end of file. */
ECanaShadow.CANBTC.bit.BRPREG = 7; //250KBPS
ECanaShadow.CANBTC.bit.TSEG2REG = 2; //250KBPS
ECanaShadow.CANBTC.bit.TSEG1REG = 10; //250KBPS
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
//HARDWARE INIT ENDS HERE
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
ECanaMboxes.MBOX16.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX16.MSGID.bit.STDMSGID = 0x200;
ECanaMboxes.MBOX17.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX17.MSGID.bit.STDMSGID = 0x201;
ECanaMboxes.MBOX18.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX18.MSGID.bit.STDMSGID = 0x202;
ECanaMboxes.MBOX19.MSGID.bit.IDE = 0;
ECanaMboxes.MBOX19.MSGID.bit.STDMSGID = 0x203;
// Configure Mailboxes 0-15 as TX, 16-31 as RX
ECanaRegs.CANMD.all = 0xFFFF0000L;
// Enable all Mailboxes */
ECanaRegs.CANME.all = 0xFFFFFFFFL;
ECanaRegs.CANME.all = 0x000F000FL;
EALLOW;
ECanaRegs.CANMIM.all = 0xFFFFFFFF;
ECanaRegs.CANOPC.all = 0xFFFF0000;
EDIS;
}
