Hi
I would like to request some more details on how thew SCI on a f28379d will handle error situations.
There is a lot of questions in this post, so please read carefully, and fell free to divide your answer in multiple replies.
I am limiting this question to the receiver part (RX), and also limit to cases using the FIFO.
First chapter is the different error status bits
I have seen other posts on this topic, but i am note sure on the conclusion.
There are three registers with error status bits
- SCIRXST
- RXERROR (FE|OE|PE)
- BRKDT (not always an error but I include it here anyway)
- FE
- OE
- PE
- SCIRXBUF
- SCIFFFE
- SCIFFPE
- SCIFFRX
- RXFFOVF
I do understand what the different error types is i.e. framing error is basically a missing stop bit a.s.o.
What is unclear is the behavior and relationship between SCIRXST->FE and SCIRXBUF->SCIFFFE.
Same for SCIRXST->PE and SCIRXBUF->SCIFFPE
Let me explain how I do understand this, and then please correct me where I am wrong.
lets imagine the SCI has received 5 bytes of data, all stored in the fifo.
We name these bytes b0 to b4, where b0 is the first to arrive on the serial line, and thus first in the fifo.
When the SCI recieved b2 it detected an parity error.
Now as I understand this.
- At the moment where b2 was received and the parity error detected, the SCIRXST->PE bit will be set, and an error IRQ will be triggered if enabled.
- The SCIRXST->PE bit will remain set until the SW issues a SW reset, by writing a 0 to the SCICTL1->SWRESET bit, followed by writing a 1 to the same bit.
- In the FIFO there is room to store this information, so the parity error is stored alongside the byte.
- When reading the bytes from the FIFO, by reading the SCIRXBUF register, I get the SCIFFPE bit as being set when, and only when, I read the b2
- As these registers is not mentioned in the to SWRESET description, I assume the error information stored in the FIFO is not affected by a sw-reset.
So after 5 reads of the SCIRXBUF register this is what i got out:
| byte |
bit 15 SCIFFFE |
bit 14 SCIFFPE |
bit 13-8 RESERVED |
bit 7-0 SAR |
| b0 | 0 | 0 | x |
data |
| b1 | 0 | 0 | x | data |
| b2 | 0 | 1 | x | invalid data |
| b3 | 0 | 0 | x | data |
| b4 | 0 | 0 | x | data |
- sidenote: Also to my understanding I have to read the SCIFFPE and the SAR, in one read, as an attempt to read only the SCIFFPE, would count as a read of that register, and pop the next value from the FIFO.
This all means that I can conclude that b0 and b1 is valid data as they where received before the error, as for b3 and b4, as they where received after the error it very much depends on other factors if they are valid, but no error was detected during the reception of those.
Now on to the next chapter of my question, data during and error.
Here i am thinking of what is shifted into the RXSHF register, and what will later turn up in the SCIRXBUF, under different error scenarios.
- On parity error I expect the received bits to be there, just marked bad by the parity error bit.
- On framing error, I expect the same, so in the case where a high->low transitions on the line, triggered the read, but the line came up again, thus no stop bit, I would se zerros in the SAR.
- if you now look at the content of RXSHF (i know it's not accessible from SW) , of all zeros including the parity, depending on parity setting this can be detected as a parity error. Will this also result in a setting of the parity error bit, or is it excluded by the framing error?
- On break detect from the manual "A break condition occurs when the SCI receiver data line (SCIRXD) remains continuously low for at least ten bits, beginning after a missing first stop bit"
- Will this "missing first stop bit" trigger a framing error, or is this excluded by the break detection?
- Again from the manual "The occurrence of a break <cut> but it does not cause the receiver buffer to be loaded.", Partly depending on the answer to the previous question. will the data before the "missing first stop bit" be shifted, and thus change RXFFST?
Last chapter, Misbehaving SW.
SW sometimes behaves different than the designers of the SCI expected :-)
How hard isthe shifting of the data from the RX-pin connected to the CTL registers et. all. ?
if the SWRESET bit or the RXENA bit is changes by SW in the middle of recieving a byte.
- will the shifting into RXSHF stop imidially?
- if no, will it be pushed to SCIRXBUF?
- if yes, will the bits already received be pushed, and will this potentially result in parity or framiong error being detected?
Are there any way besides the ones above, where misbehaving SW can trigger false PE/OE/FE errors?
If I want to change a setting like the parity bit. after first communication (cannot guarantee a silent line), what is then the recommended procedure?
Yes I do assume it involves clearing the RXENA bit, but
- Do I need to wait for anything, like shifting of a potential byte being received during the change?
- Do I need to empty the FIFO, and if I don't will the current data in the FIFO be reinterpreted, i.e. if I change the data size or parity setting?
When issuing a sw-reset, by writing a 0, followed by a write of 1 to SWRESET. Do i need to insert a pause between the write of 0 and 1?
NB: there is a typo in the reference manual "SPRUHM8I–December 2013–Revised September 2019", page 2295, line 4
"SCIFFTX controls the receive FIFO interrupt" i think it should be "SCIFFRX controls the receive FIFO interrupt"
