Other Parts Discussed in Thread: CONTROLSUITE
I have found an example for the TMS320C2000 Piccolo™ controlSTICK, but I am having trouble mapping the Piccolo instructions over to the 28335 instruction set. All I want to do is have the epm1 trigger a SOC in up-count mode. Is there a triggered adc example for this particular chip? Here is my code so far, in case there are no examples:
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // enable adc clock
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 11; // power up band gap and reference
AdcRegs.ADCTRL3.bit.ADCPWDN = 1; // power up rest of ADC
asm(" RPT#100 || NOP"); // wait 100 cycles
AdcRegs.ADCTRL1.bit.ACQ_PS = 6; // set S/H window to 6 clk cycles (117ns)
EDIS;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0; // sequencer 1 operation
AdcRegs.ADCTRL1.bit.CONT_RUN = 0; // start-stop
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0000; // convert ADC-A0 (CH0) when SEQ1 is enabled
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0001; // convert ADC-A1 (CH1) when SEQ1 is enabled
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // SEQ1 interrupt enable. This bit enables the interrupt request to CPU by INT SEQ1.
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0; // INT_SEQ1 is set at the end of every SEQ1 sequence.
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Allows SEQ1/SEQ to be started by ePWMx SOCA trigger.
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0; // immediately reset sequencer to state CONV00
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 0; // ePWM SOCA
#define period 1500 // 150MHz when PLL is set to 0xA
// 150MHz / period = PWM period
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = duty_cycle; // Set duty 50% initially; sets compare values
EPwm1Regs.TBPRD = period; // Set timer period, PWM frequency = 1 / period
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
EPwm1Regs.TBPHS.all = 0; // Time-Base Phase Register
EPwm1Regs.TBCTR = 0; // Time-Base Counter Register
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count-up mode: used for asymmetric PWM
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on CTR=Zero
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on Zero event
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on Up-Count CompareA event
After reading through several reference guides, it appears to be correct. However, it doesn't seem to be triggering. The way I am measuring this is sort of an inaccurate way of doing so. Is there some register that I can monitor while the triggering occurs? I am pretty new to working with CCS and DSP's, so any help would be very much appreciated.
-Roy
