TMS320F28377D: GPIO setting issue

Carol Guo

Part Number: TMS320F28377D

When I first used the "GpioDataRegs.GPBDAT.bit.GPIOB" function to operate gpio pin 32 to 63 output high power at the same time, I found that several gpio could not give correct feedback. However, during the program cycle, some gpio would still make level jump even if the push-pull output high level was specified, and most of them would gradually stabilize the output high level as time went by . Interestingly, I don't have this problem when I use the "GpioDataRegs.GPBSET.bit.GPIOB" function, all GPIOs output high levels . And the other gpio groups seem to have the same problem.

We did these test on different ICs and got the same result. seems like we couldn't get the correct GPIO setting by setting the "GpioDataRegs.GPBDAT.bit.GPIOB".

We'd like to know the reason, thanks

over 2 years ago

0 Omer Amir over 2 years ago

TI__Mastermind 30185 points

Hello Carol,

Do you have an idea of how many/which GPIO are not responding as expected (is it the same across all GPIO groups)? Can you also provide the GPIO configurations you use before trying to set the GPIO pins to high? Are the actual register configurations that you see in debug mode what you're expecting?

Carol Guo said:
push-pull output high level was specified

I'm not sure what you mean by this, can you clarify?

Best regards,

Omer Amir

0 Carol Guo over 2 years ago in reply to Omer Amir

Prodigy 20 points

it is the same across all GPIO groups.

"Push-pull output high level was specified"--- Set the port as the push-pull output mode.

Please find the GPIO configuration in the following code.

/###########################################################################
//
// FILE: GpioSetup.c
//
// TITLE: Device GPIO Setup
//
//! \addtogroup cpu01_example_list
//! <h1> Device GPIO Setup (GpioSetup)</h1>
//!
//! Configures the F2837xD GPIO into two different configurations
//! This code is verbose to illustrate how the GPIO could be setup.
//! In a real application, lines of code can be combined for improved
//! code size and efficiency.
//!
//! This example only sets-up the GPIO. Nothing is actually done with
//! the pins after setup.
//!
//! \b In \b general: \n
//! - All pullup resistors are enabled. For ePWMs this may not be desired.
//! - Input qual for communication ports (eCAN, SPI, SCI, I2C) is asynchronous
//! - Input qual for Trip pins (TZ) is asynchronous
//! - Input qual for eCAP and eQEP signals is synch to SYSCLKOUT
//! - Input qual for some I/O's and __interrupts may have a sampling window
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v210 $
// $Release Date: Tue Nov 1 14:46:15 CDT 2016 $
// $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"

//
// Select the example to compile in. Only one example should be set as 1
// the rest should be set as 0.
//

//
// Main
//
void main(void)
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
InitPieVectTable();
//
// Step 4. User specific code:
//
Uint32 GpioSelectPin;

#if 1

for(GpioSelectPin=0;GpioSelectPin<32;GpioSelectPin++)
{
GPIO_SetupPinOptions(GpioSelectPin, GPIO_OUTPUT,0);//CS
GPIO_SetupPinMux(GpioSelectPin,GPIO_MUX_CPU1,0);
}

for(GpioSelectPin=32;GpioSelectPin<64;GpioSelectPin++)
{
GPIO_SetupPinOptions(GpioSelectPin, GPIO_OUTPUT,0);//CS
GPIO_SetupPinMux(GpioSelectPin,GPIO_MUX_CPU1,0);
}
for(GpioSelectPin=64;GpioSelectPin<96;GpioSelectPin++)
{
GPIO_SetupPinOptions(GpioSelectPin, GPIO_OUTPUT,0);//CS
GPIO_SetupPinMux(GpioSelectPin,GPIO_MUX_CPU1,0);
}
for(GpioSelectPin=96;GpioSelectPin<128;GpioSelectPin++)
{
GPIO_SetupPinOptions(GpioSelectPin, GPIO_OUTPUT,0);//CS
GPIO_SetupPinMux(GpioSelectPin,GPIO_MUX_CPU1,0);
}
for(GpioSelectPin=128;GpioSelectPin<160;GpioSelectPin++)
{
GPIO_SetupPinOptions(GpioSelectPin, GPIO_OUTPUT,0);//CS
GPIO_SetupPinMux(GpioSelectPin,GPIO_MUX_CPU1,0);
}
for(GpioSelectPin=160;GpioSelectPin<169;GpioSelectPin++)
{
GPIO_SetupPinOptions(GpioSelectPin, GPIO_OUTPUT,0);//CS
GPIO_SetupPinMux(GpioSelectPin,GPIO_MUX_CPU1,0);
}
#endif

while(1)
{
static unsigned int GpioSetCount = 0;

GpioDataRegs.GPBDAT.bit.GPIO32 = 1;
GpioDataRegs.GPBDAT.bit.GPIO33 = 1;
GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
GpioDataRegs.GPBDAT.bit.GPIO36 = 1;
GpioDataRegs.GPBDAT.bit.GPIO37 = 1;
GpioDataRegs.GPBDAT.bit.GPIO38 = 1;
GpioDataRegs.GPBDAT.bit.GPIO39 = 1;
GpioDataRegs.GPBDAT.bit.GPIO40 = 1;
GpioDataRegs.GPBDAT.bit.GPIO41 = 1;
GpioDataRegs.GPBDAT.bit.GPIO42 = 1;
GpioDataRegs.GPBDAT.bit.GPIO43 = 1;
GpioDataRegs.GPBDAT.bit.GPIO44 = 1;
GpioDataRegs.GPBDAT.bit.GPIO45 = 1;
GpioDataRegs.GPBDAT.bit.GPIO46 = 1;
GpioDataRegs.GPBDAT.bit.GPIO47 = 1;
GpioDataRegs.GPBDAT.bit.GPIO48 = 1;
GpioDataRegs.GPBDAT.bit.GPIO49 = 1;
GpioDataRegs.GPBDAT.bit.GPIO50 = 1;
GpioDataRegs.GPBDAT.bit.GPIO51 = 1;
GpioDataRegs.GPBDAT.bit.GPIO52 = 1;
GpioDataRegs.GPBDAT.bit.GPIO53 = 1;
GpioDataRegs.GPBDAT.bit.GPIO54 = 1;
GpioDataRegs.GPBDAT.bit.GPIO55 = 1;
GpioDataRegs.GPBDAT.bit.GPIO56 = 1;
GpioDataRegs.GPBDAT.bit.GPIO57 = 1;
GpioDataRegs.GPBDAT.bit.GPIO58 = 1;
GpioDataRegs.GPBDAT.bit.GPIO59 = 1;
GpioDataRegs.GPBDAT.bit.GPIO60 = 1;
GpioDataRegs.GPBDAT.bit.GPIO61 = 1;
GpioDataRegs.GPBDAT.bit.GPIO62 = 1;
GpioDataRegs.GPBDAT.bit.GPIO63 = 1;

GpioSetCount++;
}
}

// GpioDataRegs.GPADAT.bit.GPIO1 = 1;
// GpioDataRegs.GPADAT.bit.GPIO2 = 1;
// GpioDataRegs.GPADAT.bit.GPIO3 = 1;
// GpioDataRegs.GPADAT.bit.GPIO4 = 1;
// GpioDataRegs.GPADAT.bit.GPIO5 = 1;
// GpioDataRegs.GPADAT.bit.GPIO6 = 1;
// GpioDataRegs.GPADAT.bit.GPIO7 = 1;
// GpioDataRegs.GPADAT.bit.GPIO8 = 1;
// GpioDataRegs.GPADAT.bit.GPIO9 = 1;
// GpioDataRegs.GPADAT.bit.GPIO10 = 1;
// GpioDataRegs.GPADAT.bit.GPIO11 = 1;
// GpioDataRegs.GPADAT.bit.GPIO12 = 1;
// GpioDataRegs.GPADAT.bit.GPIO13 = 1;
// GpioDataRegs.GPADAT.bit.GPIO14 = 1;
// GpioDataRegs.GPADAT.bit.GPIO15 = 1;
// GpioDataRegs.GPADAT.bit.GPIO16 = 1;
// GpioDataRegs.GPADAT.bit.GPIO17 = 1;
// GpioDataRegs.GPADAT.bit.GPIO18 = 1;
// GpioDataRegs.GPADAT.bit.GPIO19 = 1;
// GpioDataRegs.GPADAT.bit.GPIO20 = 1;
// GpioDataRegs.GPADAT.bit.GPIO21 = 1;
// GpioDataRegs.GPADAT.bit.GPIO22 = 1;
// GpioDataRegs.GPADAT.bit.GPIO23 = 1;
// GpioDataRegs.GPADAT.bit.GPIO24 = 1;
// GpioDataRegs.GPADAT.bit.GPIO25 = 1;
// GpioDataRegs.GPADAT.bit.GPIO26 = 1;
// GpioDataRegs.GPADAT.bit.GPIO27 = 1;
// GpioDataRegs.GPADAT.bit.GPIO28 = 1;
// GpioDataRegs.GPADAT.bit.GPIO29 = 1;
// GpioDataRegs.GPADAT.bit.GPIO30 = 1;
// GpioDataRegs.GPADAT.bit.GPIO31 = 1;

// GpioDataRegs.GPBSET.bit.GPIO32 = 1;
// GpioDataRegs.GPBSET.bit.GPIO33 = 1;
// GpioDataRegs.GPBSET.bit.GPIO34 = 1;
// GpioDataRegs.GPBSET.bit.GPIO35 = 1;
// GpioDataRegs.GPBSET.bit.GPIO36 = 1;
// GpioDataRegs.GPBSET.bit.GPIO37 = 1;
// GpioDataRegs.GPBSET.bit.GPIO38 = 1;
// GpioDataRegs.GPBSET.bit.GPIO39 = 1;
// GpioDataRegs.GPBSET.bit.GPIO40 = 1;
// GpioDataRegs.GPBSET.bit.GPIO41 = 1;
// GpioDataRegs.GPBSET.bit.GPIO42 = 1;
// GpioDataRegs.GPBSET.bit.GPIO43 = 1;
// GpioDataRegs.GPBSET.bit.GPIO44 = 1;
// GpioDataRegs.GPBSET.bit.GPIO45 = 1;
// GpioDataRegs.GPBSET.bit.GPIO46 = 1;
// GpioDataRegs.GPBSET.bit.GPIO47 = 1;
// GpioDataRegs.GPBSET.bit.GPIO48 = 1;
// GpioDataRegs.GPBSET.bit.GPIO49 = 1;
// GpioDataRegs.GPBSET.bit.GPIO50 = 1;
// GpioDataRegs.GPBSET.bit.GPIO51 = 1;
// GpioDataRegs.GPBSET.bit.GPIO52 = 1;
// GpioDataRegs.GPBSET.bit.GPIO53 = 1;
// GpioDataRegs.GPBSET.bit.GPIO54 = 1;
// GpioDataRegs.GPBSET.bit.GPIO55 = 1;
// GpioDataRegs.GPBSET.bit.GPIO56 = 1;
// GpioDataRegs.GPBSET.bit.GPIO57 = 1;
// GpioDataRegs.GPBSET.bit.GPIO58 = 1;
// GpioDataRegs.GPBSET.bit.GPIO59 = 1;
// GpioDataRegs.GPBSET.bit.GPIO60 = 1;
// GpioDataRegs.GPBSET.bit.GPIO61 = 1;
// GpioDataRegs.GPBSET.bit.GPIO62 = 1;
// GpioDataRegs.GPBSET.bit.GPIO63 = 1;

// GpioDataRegs.GPBDAT.bit.GPIO32 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO33 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO34 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO35 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO36 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO37 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO38 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO39 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO40 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO41 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO42 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO43 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO44 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO45 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO46 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO47 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO48 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO49 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO50 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO51 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO52 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO53 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO54 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO55 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO56 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO57 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO58 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO59 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO60 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO61 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO62 = 1;
// GpioDataRegs.GPBDAT.bit.GPIO63 = 1;
//
// GpioDataRegs.GPCDAT.bit.GPIO64 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO65 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO66 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO67 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO68 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO69 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO70 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO71 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO72 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO73 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO74 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO75 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO76 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO77 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO78 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO79 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO80 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO81 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO82 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO83 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO84 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO85 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO86 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO87 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO88 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO89 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO90 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO91 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO92 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO93 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO94 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO95 = 1;
//
// GpioDataRegs.GPDDAT.bit.GPIO96 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO97 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO98 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO99 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO100 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO101 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO102 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO103 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO104 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO105 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO106 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO107 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO108 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO109 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO110 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO111 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO112 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO113 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO114 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO115 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO116 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO117 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO118 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO119 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO120 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO121 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO122 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO123 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO124 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO125 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO126 = 1;
// GpioDataRegs.GPDDAT.bit.GPIO127 = 1;
//
// GpioDataRegs.GPEDAT.bit.GPIO128 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO129 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO130 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO131 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO132 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO133 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO134 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO135 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO136 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO137 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO138 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO139 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO140 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO141 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO142 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO143 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO144 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO145 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO146 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO147 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO148 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO149 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO150 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO151 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO152 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO153 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO154 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO155 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO156 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO157 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO158 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO159 = 1;
//
// GpioDataRegs.GPFDAT.bit.GPIO160 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO161 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO162 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO163 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO164 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO165 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO166 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO167 = 1;
// GpioDataRegs.GPFDAT.bit.GPIO168 = 1;
// GpioDataRegs.GPEDAT.bit.GPIO149 = 1;



// GpioDataRegs.GPCDAT.bit.GPIO75 = 1;//~(GpioDataRegs.GPCDAT.bit.GPIO75);
// GpioDataRegs.GPCSET.bit.GPIO76 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO76 = 1;
// GpioDataRegs.GPCDAT.bit.GPIO77 = 1;
// GpioDataRegs.GPCDAT.all|=0x3800;




//}

//
// Gpio_setup1 - Basic Pinout.
// This basic pinout includes:
// PWM1-3, ECAP1, ECAP2, TZ1-TZ4, SPI-A, EQEP1, SCI-A, I2C
// and a number of I/O pins
//



#if EXAMPLE1

//
// This example is a basic pinout
//
Gpio_setup1();

#endif // - EXAMPLE1

#if EXAMPLE2

//
// This example is a communications pinout
//
Gpio_setup2();

#endif

void Gpio_setup1(void)
{
//
// These can be combined into single statements for improved
// code efficiency.
//

//
// Enable PWM1-3 on GPIO0-GPIO5
//
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B

//
// Enable an GPIO output on GPIO6, set it high
//
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6
GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output

//
// Enable eCAP1 on GPIO7
//
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLOUT
InputXbarRegs.INPUT7SELECT = 7; // GPIO7 = ECAP1

//
// Enable GPIO outputs on GPIO8 - GPIO11, set it high
//
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8
GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output

GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9
GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9
GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output

GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10
GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO10 = output

GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11
GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output

//
// Enable Trip Zone inputs on GPIO12 - GPIO14
//
GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0; // Enable pullup on GPIO12
GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0; // Enable pullup on GPIO13
GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pullup on GPIO14
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // asynch input
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // asynch input
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // asynch input
InputXbarRegs.INPUT1SELECT = 12; // GPIO12 = TZ1
InputXbarRegs.INPUT2SELECT = 13; // GPIO13 = TZ2
InputXbarRegs.INPUT3SELECT = 14; // GPIO14 = TZ3

//
// Enable SPI-A on GPIO16 - GPIO19
//
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA

//
// Enable EQEP1 on GPIO20 - GPIO23
//
GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0; // Enable pullup on GPIO20
GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0; // Enable pullup on GPIO21
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO22
GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pullup on GPIO23
GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Synch to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Synch to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Synch to SYSCLKOUT
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Synch to SYSCLKOUT
GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // GPIO20 = EQEP1A
GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // GPIO21 = EQEP1B
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // GPIO22 = EQEP1S
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // GPIO23 = EQEP1I

//
// Enable eCAP1 on GPIO24
//
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT
InputXbarRegs.INPUT7SELECT = 24; // GPIO24 = ECAP1

//
// Set input qualifcation period for GPIO25 & GPIO26
//
GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2
GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples
GpioCtrlRegs.GPAQSEL2.bit.GPIO26=2; // 6 samples

//
// Make GPIO25 the input source for XINT1
//
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25
GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input
GPIO_SetupXINT1Gpio(25); // XINT1 connected to GPIO25

//
// Make GPIO26 the input source for XINT2
//
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26
GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input
GPIO_SetupXINT2Gpio(26); // XINT2 connected to GPIO26

//
// Make GPIO27 wakeup from HALT/STANDBY Low Power Modes
//
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27
GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input
CpuSysRegs.GPIOLPMSEL0.bit.GPIO27=1; // GPIO27 will wake the device
CpuSysRegs.LPMCR.bit.QUALSTDBY = 2; // Qualify GPIO27 by 2 OSCCLK
// cycles before waking the device
// from STANDBY

//
// Enable SCI-A on GPIO28 - GPIO29
//
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA

//
// Enable CAN-A on GPIO30 - GPIO31
//
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31
GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // Asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA

//
// Enable I2C-A on GPIO32 - GPIO33
//
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33
GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; // Asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA

//
// Make GPIO34 an input
//
GpioCtrlRegs.GPBPUD.bit.GPIO34 = 0; // Enable pullup on GPIO34
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input
EDIS;
}

//
// Gpio_setup2 - Communications Pinout.
// This basic communications pinout includes:
// PWM1-3, CAP1, CAP2, SPI-A, SPI-B, CAN-A, SCI-A and I2C
// and a number of I/O pins
//
void Gpio_setup2(void)
{
//
// Enable PWM1-3 on GPIO0-GPIO5
//
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; // Enable pullup on GPIO0
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; // Enable pullup on GPIO1
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; // Enable pullup on GPIO2
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pullup on GPIO3
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0; // Enable pullup on GPIO4
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pullup on GPIO5
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO0 = PWM1A
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = PWM1B
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO2 = PWM2A
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO3 = PWM2B
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO4 = PWM3A
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO5 = PWM3B

//
// Enable an GPIO output on GPIO6
//
GpioCtrlRegs.GPAPUD.bit.GPIO6 = 0; // Enable pullup on GPIO6
GpioDataRegs.GPASET.bit.GPIO6 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 0; // GPIO6 = GPIO6
GpioCtrlRegs.GPADIR.bit.GPIO6 = 1; // GPIO6 = output

//
// Enable eCAP1 on GPIO7
//
GpioCtrlRegs.GPAPUD.bit.GPIO7 = 0; // Enable pullup on GPIO7
GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Synch to SYSCLKOUT
InputXbarRegs.INPUT7SELECT = 7; // GPIO7 = ECAP1

//
// Enable GPIO outputs on GPIO8 - GPIO11
//
GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pullup on GPIO8
GpioDataRegs.GPASET.bit.GPIO8 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0; // GPIO8 = GPIO8
GpioCtrlRegs.GPADIR.bit.GPIO8 = 1; // GPIO8 = output

GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pullup on GPIO9
GpioDataRegs.GPASET.bit.GPIO9 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 = GPIO9
GpioCtrlRegs.GPADIR.bit.GPIO9 = 1; // GPIO9 = output

GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pullup on GPIO10
GpioDataRegs.GPASET.bit.GPIO10 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 0; // GPIO10 = GPIO10
GpioCtrlRegs.GPADIR.bit.GPIO10 = 1; // GPIO10 = output

GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pullup on GPIO11
GpioDataRegs.GPASET.bit.GPIO11 = 1; // Load output latch
GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 0; // GPIO11 = GPIO11
GpioCtrlRegs.GPADIR.bit.GPIO11 = 1; // GPIO11 = output

//
// Enable SPI-B on GPIO22 - GPIO25
//
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO12 (SPISIMOB)
GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pullup on GPIO13 (SPISOMIB)
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO14 (SPICLKB)
GpioCtrlRegs.GPAPUD.bit.GPIO25 = 0; // Enable pullup on GPIO15 (SPISTEB)
GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; // asynch input
GpioCtrlRegs.GPAGMUX2.bit.GPIO22 = 1; // Set Group Mux
GpioCtrlRegs.GPAGMUX2.bit.GPIO23 = 1; // Set Group Mux
GpioCtrlRegs.GPAGMUX2.bit.GPIO24 = 1; // Set Group Mux
GpioCtrlRegs.GPAGMUX2.bit.GPIO25 = 1; // Set Group Mux
GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; // GPIO22 = SPICLKB
GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; // GPIO23 = SPISTEB
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // GPIO24 = SPISIMOB
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // GPIO25 = SPISOMIB

//
// Enable SPI-A on GPIO16 - GPIO19
//
GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pullup on GPIO16 (SPICLKA)
GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pullup on GPIO17 (SPIS0MIA)
GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pullup on GPIO18 (SPICLKA)
GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pullup on GPIO19 (SPISTEA)
GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // asynch input
GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // GPIO16 = SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // GPIO17 = SPIS0MIA
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // GPIO18 = SPICLKA
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // GPIO19 = SPISTEA

//
// Enable eCAP1 on GPIO24
//
GpioCtrlRegs.GPAPUD.bit.GPIO24 = 0; // Enable pullup on GPIO24 (ECAP1)
GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Synch to SYSCLKOUT
InputXbarRegs.INPUT7SELECT = 24; // GPIO24 = ECAP1

//
// Set input qualification period for GPIO25 & GPIO26 inputs
//
GpioCtrlRegs.GPACTRL.bit.QUALPRD3=1; // Qual period = SYSCLKOUT/2
GpioCtrlRegs.GPAQSEL2.bit.GPIO25=2; // 6 samples
GpioCtrlRegs.GPAQSEL2.bit.GPIO26=1; // 3 samples

//
// Make GPIO25 the input source for XINT1
//
GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 0; // GPIO25 = GPIO25
GpioCtrlRegs.GPADIR.bit.GPIO25 = 0; // GPIO25 = input
GPIO_SetupXINT1Gpio(25); // XINT1 connected to GPIO25

//
// Make GPIO26 the input source for XINT2
//
GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 0; // GPIO26 = GPIO26
GpioCtrlRegs.GPADIR.bit.GPIO26 = 0; // GPIO26 = input
GPIO_SetupXINT2Gpio(26); // XINT2 connected to GPIO26

//
// Make GPIO27 wakeup from HALT/STANDBY Low Power Modes
//
GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 0; // GPIO27 = GPIO27
GpioCtrlRegs.GPADIR.bit.GPIO27 = 0; // GPIO27 = input
CpuSysRegs.GPIOLPMSEL0.bit.GPIO27=1; // GPIO27 will wake the device
CpuSysRegs.LPMCR.bit.QUALSTDBY = 2; // Qualify GPIO27 by 2 OSCCLK
// cycles before waking the device
// from STANDBY

//
// Enable SCI-A on GPIO28 - GPIO29
//
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pullup on GPIO28
GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // GPIO28 = SCIRXDA
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pullup on GPIO29
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // GPIO29 = SCITXDA

//
// Enable CAN-A on GPIO30 - GPIO31
//
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pullup on GPIO30
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // GPIO30 = CANTXA
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pullup on GPIO31
GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 3; // asynch input
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // GPIO31 = CANRXA

//
// Enable I2C-A on GPIO32 - GPIO33
//
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO32
GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; // Enable pullup on GPIO33
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input
GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; // asynch input
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; // GPIO32 = SDAA
GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; // GPIO33 = SCLA

//
// Make GPIO34 an input
//
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; // Enable pullup on GPIO34
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0; // GPIO34 = GPIO34
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0; // GPIO34 = input

EDIS;
}

//
// End of file
//

Fig 1. "GpioDataRegs.GPBDAT.bit.GPIOB" first running

Fig 2."GpioDataRegs.GPBDAT.bit.GPIOB" several running

Fig3 GpioDataRegs.GPBSET.bit.GPIOB" first running

0 Omer Amir over 2 years ago in reply to Carol Guo

TI__Mastermind 30185 points

Hello Carol,

Please do not just dump your code as plain text, this makes it very difficult to read through posts for debugging.

I did not realize you were setting the pins one-by-one, is there any difference if you just set all the GPIO using GpioDataRegs.GPBDAT.all = 0xFFFFFFFF?

Carol Guo said:
Fig 2."GpioDataRegs.GPBDAT.bit.GPIOB" several running

How many iterations is several? Have you tried adding a delay function for 1 ms to see if that changed anything?

Best regards,

Omer Amir

0 Carol Guo over 2 years ago in reply to Omer Amir

Prodigy 20 points

Hi, Omer.

Thanks for your reply.

Sorry for the code dumping mistake.

When setting the GPIO Pins one-by-one, Same issue appears.

We would like to know the difference between these two instructions, and is there any reason that might cause unwanted results when using command "GpioDataRegs.GPBSET.bit.GPIOB".

0 Omer Amir over 2 years ago in reply to Carol Guo

TI__Mastermind 30185 points

Hello Carol,

I double-checked with the device manual and there does seem to be something covering a similar issue. In section 8.3 Digital General-Purpose I/O Control, the description for the GPyDAT registers states that writing to the same GPyDAT group can cause a lag in the reflected value on the pin. The solution is to either put NOPs between instructions or use the GPySET/GPyCLEAR/GPyTOGGLE registers, which seems to be proven by what your earlier post stated. If you want to write to multiple pins in the format you have above, then you would need to use GPBSET to do this. EDIT: I confirmed with a software expert that if you intend to use GPBDAT to set the pins, using "GpioDataRegs.GPBDAT.all = 0xFFFFFFFF" can replace the numerous lines you used instead (this will write all the bits with respect to the lag).

Carol Guo said:
We would like to know the difference between these two instructions, and is there any reason that might cause unwanted results when using command "GpioDataRegs.GPBSET.bit.GPIOB".

Essentially GPBSET can only be used to set a GPIO output pin, i.e. you cannot clear the output pin and trying to read GPBSET always reads back 0. If GPBDAT is not working as intended, you would need to use GPBSET to set the output pin and GPBCLEAR to clear it, but otherwise it should act the same.

Best regards,

Omer Amir

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28377D: GPIO setting issue