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TMS320F28379D: EMIF Interfacting with FRAM

user _ti28379d
Prodigy 190 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Hi All,

I am currently working on the following examples:-

1.emif_ex1_16bit_asram 

2. emif_ex2_16bit_asram _codemem

Hardware wise all the pins of FRAM are overlapping with EMIF1 in our personalized mcu board .Following are the changes I made:

1.Changed the starting address and length according to cmd file

#define ASRAM_CS2_START_ADDR 0x00100000

#define ASRAM_CS2_SIZE 0x00200000

 EMIF1_CS2n       : origin = 0x00100000, length = 0x00200000

2. Change GPIODQM to address lines.

GPIO_setPinConfig(GPIO_88_EM1A15);
GPIO_setPinConfig(GPIO_89_EM1A16);
GPIO_setPinConfig(GPIO_90_EM1A17);

The problem is test status global is showing test fail and error counter is 4

\b testStatusGlobal - Equivalent to \b TEST_PASS if test finished
//! correctly, else the value is set to \b TEST_FAIL
//! - \b errCountGlobal - Error counter

Can anyone guide me how to work on these examples and how to rectify the problem.

Regards

Drishti

  • 0
    TI__Guru* 95315 points

    Drishti,

        All C2000ware examples are tested examples. Your start address and size values are correct. If the examples fail, it is very likely there is either a H/W issue on your board or there is a timing issue. You may be able to spot a timing issue by slowing down your EMIF clock. You can also single-step through your code to find out which of the 3 functions [walkMemAddr(), walkMemData() & accessMemData()] is failing. If you have a scope or a logic analyzer, you can measure the waveforms to ensure datasheet timing requirements are not violated. Without access to your H/W, this is the best debug support I can provide.

  • 0 in reply to Hareesh Janakiraman
    Prodigy 190 points

    Hello Sir,

    I ran the example for 32 bit address lines and I am able to see the lower 16 bits correctly.The issue is according to 16 bit config ba1 should be synchronized to address0 of SRAM but in my hardware  a0 of emif is synchronized with address0 of SRAM . Is there a way out to mask the upper 16 bits & make it compatible with 16 bit configuration while using the same hardware.

  • 0 in reply to user _ti28379d
    TI__Guru* 95315 points

    Drishti,

         Hopefully, this thread answers your question: