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TMS320F28035: ADC pin and block failures, wondering if clamping current is to blame

Part Number: TMS320F28035

Hello,

I have a design in the field that we're experiencing a number of issues with. As I've been investigating potential issues with the design, I've noticed that when the power supplies for the TMS320F28035 are switched off, the supply rails, digital and analog 3.3V appear to be hovering around 0.4-0.6 V. I suspect that the supply rails are being held to 0.4-0.6V by ADC inputs that are likely conducting through the clamping diodes of the  TMS320F28035. By design, series resistance limits the maximum DC current into any of these ADC pins to be less than 110 uA. I noticed that here's ~ 5.7 nF (nominal) of MLCC capacitance on these pins, and if the ADC pins voltage were say 1.7V while the VDDA supply source was being powered down, then as VDDA potential dropped below the V_F of the clamping diode, current would conduct from the analog input pin, through the diode, and onto the analog supply rail, with very little series resistance to limit the current. However the VDDA and VDDIO supplies both have large capacitors (severs uF) by comparison to the 5.7 nF filter caps on the ADC input pins, so I'd expect both the VDDA rail and the analog input pins to decrease in unison, with the analog input pin offset by the forward voltage drop of the clamping diode, until a steady state is reached where the small (<100 uA) current per analog input pin is flowing through the clamping diode onto the VDDA/VDDIO rails and through any impedance on those rails into ground. If my understanding is correct, then I don't believe the design is violating the abs max of +/- 20 mA of clamping current, and note 3 in the abs max seciton of the datasheet states: "Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and impact other electrical specifications.". Again, I do not think the design is violating the +/- 2mA per pin limit, however, it is continuously flowing current through the clamp diodes, and the VDDIO/VDDA supply voltages are rising to 0.4-0.6V. Is the scenario I'm describing something that we should be concerned could damage the TMS320 part? I've included a simplified schematic diagram for illustration, the scenario is when SW1 is open, the A3V3 and D3V3 rails remain around 0.4-0.6V, I believe due to current flowing from ADC pins with structures similar to that shown below.

Thanks for your support!

  • Hi Neal,

    In your simplified schematic, are you seeing the residual voltage on the actual ADC_IN signals? Or just the A3V3 and D3V3 supply rails?

    Best,

    Kevin

  • Hi Kevin,

    Thanks for the clarifying question. The residual voltage is seen on the ACD_IN signals. I don't have a measurement for the voltage that would correlate with the simplified schematic, I'll be able to grab that later this week, but on a different ADC input pin, which has the exact same resistor divider circuit, but is sourced by ~ 23V, I was measuring about 0.68 V at the ADC input pin, compared to the ~ 0.83 V I would've expected based solely on the resistor divider. In that case, from V=IR I calculated ~47 uA of current through the 475k resistor, and about 38 uA through the 17.8k resistor, suggesting about 9 uA of current flowing through the ADC input pin.

    Thanks,

    Neal

  • Neal,

    What you describe sounds like it will not be a problem.  You could scope the VDDA/VDDIO and ADC input lines to see the decay on a power down to confirm.  I would only be worried about the filter cap causing a >20mA spike if the VDDA/VDDIO were a hard and fast power down, which is unlikely.  Like you mentioned, it is more likely the ADC pin will track with the slower supply decay as the internal clamping diode activates.

    Best regards,

    Jason

  • Neal,

              Wanted to bring to your attention the following note in the datasheet:

    VDDA=0 when device is unpowered, but you are presenting 1.73v into the ADC input. Based on the datasheet note above, it is a violation.

  • Hi Hareesh,

    Thank you for bringing this to my attention. I agree that the design violates the power sequencing note. Is there any way to get support with more details on what the unpredictable behavior might be? We have product in the field with this design, so I am trying to understand the implications of this violation.

    Thanks,

    Neal

  • Neal,

           Let me discuss this with Jason and get back to you. Will try and respond by Friday.

  • Neal,

        I have sent you a friendship request. Please accept it so that we can discuss the design details.