• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 83 subscribers
  • Views 217 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS320F280039C: Sysconfig does not seem to generate shadow for deadband registers

TMS320F280039C: Clarify Driverlib API "EPWM_setDeadBandControlShadowLoadMode()"

Wayne Huang
Genius 16395 points
Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE

Dear champs,

I am asking this for our customer.

In C2000ware V4.03 driverlib, 

 EPWM_setDeadBandControlShadowLoadMode(myEPWM1_BASE, EPWM_DB_LOAD_ON_CNTR_ZERO);

seems to clear DBCTL.OUT_MODE, which is not expected!!

See CCS step-by-step debug on watch window,

Before running EPWM_setDeadBandControlShadowLoadMode(myEPWM1_BASE, EPWM_DB_LOAD_ON_CNTR_ZERO);

After running EPWM_setDeadBandControlShadowLoadMode(myEPWM1_BASE, EPWM_DB_LOAD_ON_CNTR_ZERO);

Looking into its source,

static inline void
EPWM_setDeadBandControlShadowLoadMode(uint32_t base,
                                      EPWM_DeadBandControlLoadMode loadMode)
{
    //
    // Check the arguments
    //
    ASSERT(EPWM_isBaseValid(base));

    //
    // Enable the shadow mode and setup the load event
    //
    HWREGH(base + EPWM_O_DBCTL2) =
          ((HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_LOADDBCTLMODE_M) |
           (EPWM_DBCTL2_SHDWDBCTLMODE | (uint16_t)loadMode));
}

Does loadMode need shift like this "(uint16_t)loadMode << EPWM_DBCTL2_LOADREDMODE_S" ?

Would you please check this?

  • 0
    TI__Expert 7120 points

    Hi Wayne,


    When the shadow mode is enabled, the value to be written in bits 0:5 for DBCTL register are expected to be written after the shadow mode is enabled. The order that is followed in the code snippet that you've shared doesn't seem to be correct. The customer is first trying to write directly to those bits and later enabling the shadow mode for the same.

    I am not too sure on why it is clearing, I can check with the design owner for that. But anyways, the way user should configure is different from how it is currently configured in the code snippet that you've shared.

    Thanks,

    Aditya

  • 0 in reply to Aditya Dholakia
    TI__Genius 16395 points

    Dear Aditya,

    I just tried with bit-field based codes and found the same result, so it has nothing to do with driverlib.

    Instead, when I write 1 to DBCTL2.SHDWDBCTLMODE, it always clears DBCTL.DBCTL.OUT_MODE and POLSEL, which is not documented in TRM.

    If possible, would you please help confirm it?

    Then, we should ask TRM owner to update it so that the user knows they should set DBCTL2.SHDWDBCTLMODE first and then modify DBCTL.

    So far, I am implementing it in this order and it works well.

     

  • 0 in reply to Wayne Huang
    TI__Expert 7120 points

    Yes, I too observed the same thing. As far as the use case is concerned, it shouldn't be an issue for the user since anyways the shadow configuration is supposed to be enabled prior to loading values in DBCTL[0:5] bits.

    I am following up with the design team to see if this is a known item which can be documented or not.

    Thanks,

    Aditya