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TMS320F28386D: PLL clock

W Z
Expert 2350 points
Part Number: TMS320F28386D

Does  CPU1 and CPU2 share one PLL clock?

Or Each of them has the private PLL clock?  (TMS320F28386D)

  • 0
    Expert 2350 points

    Due to it makes us confused that When I check the  AUXPLLSTS Register by debug. I shows different result between CPU1 and CPU2.

  • 0 in reply to W Z
    TI__Genius 11071 points

    Hello,

    Clock configuration registers cannot be simultaneously accessed by both CPUs. By default, they are configured using CPU1. However, CPU2 can grab control of the registers if required using the clock configuration semaphore (CLKSEM). For more information, please see "C28x System Control and Interrupts > Clock Configuration Semaphore" in the F2838x Technical Reference Manual.

    CPU1 and CPU2 are clocked by SYSPLL. AUXPLL is used for the Connectivity Manager subsystem, and some external interface clocks like USB, EtherCAT and CAN. That said, each C28x CPU subsystem has its own clock domains (CPU1.CPUCLK/CPU1.SYSCLK and CPU2.CPUCLK/CPU2.SYSCLK), but these are derived from the same PLLSYSCLK.

    Best regards,
    Ibukun

  • 0 in reply to Ibukun Olumuyiwa
    Expert 2350 points

    Yes, I try invoke  SysCtl_setSemOwner(SYSCTL_CPUSEL_CPU2);  It works now.

    But I am confused that CPU2 only want the read access in the default semaphore  but this mechanism forbid.

     

  • +1 in reply to W Z
    TI__Genius 11071 points

    CPU2 cannot read the registers while they are owned by CPU1. They will read as 0. The peripheral bus access is exclusive to the owner CPU.