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TMS320F28377D: EMIF request arbitration details

Part Number: TMS320F28377D

Hello,

I am looking for details about the arbitration of requests in the TMS320F28377D EMIF1.

From SPRUHM8I document, §25.5.2 EMIF Requests, the following 4 sources are possible:

CPU1
CPU1.DMA
CPU2
CPU2.DMA

From SPRUHM8I document, §25.5.13 Priority and Arbitration, arbitration among requests from different sources
within the microcontroller are (only asynchronous mode, SDRAM not used) in the order

1 - Read request

2 - Write request

How arbitration is managed when 2 read requests form 2 differents sources are presented within the microcontroller to EMIF ? There is a priority by source ?  How it is managed (fixed, round robin) ?

Thank you