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TMS320F280048-Q1: PSFB CDR converter with PCMC: Unmatched peak-current waveform at primary

Gokhan G.
Intellectual 755 points
Part Number: TMS320F280048-Q1
Other Parts Discussed in Thread: TIDM-02009, PMP23126

Hi Gus,

I loaded my PCMC software to my PSFB CDR board. I drive switches for TR-LEAD topology, QD ends power transfer interval. I investigated the software of TIDM-02009, PMP23126.

I'm testing the only inner loop performance so I changed the MAXREF value via UART and change the peak current set value.

I obtained following unequal current waveforms on Lext. By the way, I use diode bridge to rectify the output of CT current.

Schematic is as below.

Oscilloscope colours is as below:

GREEN: Current on CT,                GRAY: ADC Signal - Output of CT,

YELLOW: Primary Voltage of Transformer,                 BLUE: 2B VDS, 

RED: 3A VDS

Waveform#1 is as below. 

Vin=250 Iin=1.1 Vout=7.9 Iout=31.35, Load is, CR mode=0,25ohm

 

Waveform#2 is as below. 

Vin=250 Iin=2.5 Vout=12.09 Iout=48.12, CR mode=0,25ohm

Waveform #3 is as below, I removed clamping diodes and get following waveforms.

Vin=250V, Iin=1.8, Vout=10.09, Iout=40,CR mode=0,25ohm

PWM8 generates SYNCPER signal at all ZERO and I use PWM1 and PWM2 to drive power switches.

void SYNC_init(void)
{
    SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT);
    //
    // For EPWM1, the sync input is: SYSCTL_SYNC_IN_SRC_EXTSYNCIN1
    //
    SysCtl_setSyncInputConfig(SYSCTL_SYNC_IN_EPWM4, SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT);
    SysCtl_setSyncInputConfig(SYSCTL_SYNC_IN_EPWM7, SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT);

}

void InitHRPWM1(void)
{
    EPWM_setPeriodLoadMode(EPWM1_BASE, EPWM_PERIOD_SHADOW_LOAD);

    // Time-Base Submodule Configurations
    EPWM_setClockPrescaler(EPWM1_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBasePeriod(EPWM1_BASE, PeriodValue);
    EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
    EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);

    //
    // Phase Configuration and Set
    // Configure PWM base1 as master
    // SetPhaseShift as zero!
    //
    EPWM_disablePhaseShiftLoad(EPWM1_BASE);
    EPWM_setPhaseShift(EPWM1_BASE, 0U);
    EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);
}

void InitHRPWM2(void)
{
    // MISC. Period Load Mode
    EPWM_setPeriodLoadMode(EPWM2_BASE, EPWM_PERIOD_SHADOW_LOAD);

    // Time-Base Submodule Configurations
    EPWM_setClockPrescaler(EPWM2_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBasePeriod(EPWM2_BASE, PeriodValue);
    EPWM_setTimeBaseCounter(EPWM2_BASE, 0U);
    EPWM_setTimeBaseCounterMode(EPWM2_BASE, EPWM_COUNTER_MODE_UP_DOWN);

    //
    // Phase Configuration and Set
    // Configure PWM base2 as slave
    // SetPhaseShift = Value*TBCLK = Value*10nsec
    //
    EPWM_enablePhaseShiftLoad(EPWM2_BASE);
    EPWM_setSyncOutPulseMode(EPWM2_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);

    EPWM_setPhaseShift(EPWM2_BASE, 2); // Value*TBCLKs Phase-Shift is Set
    EPWM_setCountModeAfterSync(EPWM2_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
}

    void InitHRPWM8(void)
{
    EPWM_setPeriodLoadMode(EPWM8_BASE, EPWM_PERIOD_SHADOW_LOAD);
    // Time-Base Submodule Configurations
    EPWM_setClockPrescaler(EPWM8_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBasePeriod(EPWM8_BASE, PeriodValue -1);
    EPWM_setTimeBaseCounter(EPWM8_BASE, 0);
    EPWM_setTimeBaseCounterMode(EPWM8_BASE, EPWM_COUNTER_MODE_UP);

    //
    // Phase Configuration and Set
    // Configure PWM base3 as slave
    // SetPhaseShift = Value*TBCLK = Value*10nsec
    EPWM_enablePhaseShiftLoad(EPWM8_BASE);
    EPWM_setPhaseShift(EPWM8_BASE, 2); // Will be clarified later on!
    EPWM_setSyncOutPulseMode(EPWM8_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_setCountModeAfterSync(EPWM8_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
    
    HRPWM_setSyncPulseSource(EPWM8_BASE,HRPWM_PWMSYNC_SOURCE_ZERO);
}

void PSFB_HAL_initCmpssPCMC(void)
{
    CMPSS_configHighComparator(CMPSS5_BASE,CMPSS_INSRC_DAC);
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_5,0);
    CMPSS_configDAC(CMPSS5_BASE, CMPSS_DACREF_VDDA |CMPSS_DACVAL_PWMSYNC | CMPSS_DACSRC_RAMP);
    CMPSS_configRamp(CMPSS5_BASE,0,0,0U,8U,true);
    CMPSS_initFilterHigh(CMPSS5_BASE);
    CMPSS_configOutputsHigh(CMPSS5_BASE,
                CMPSS_TRIP_ASYNC_COMP | CMPSS_TRIPOUT_ASYNC_COMP);

    // Clear the latched comparator events
    CMPSS_clearFilterLatchHigh(CMPSS5_BASE);
    CMPSS_clearFilterLatchLow(CMPSS5_BASE);

    // Enables the CMPSS module.
    CMPSS_enableModule(CMPSS5_BASE);
    DEVICE_DELAY_US(500);

Could you please help on why I got unequal primary peak current levels on ADC voltage?

Could you please investigate my related software lines?

  • 0
    TI__Mastermind 29521 points

    Hi Gokhan,

    There is a lot of information and code here. It will take a while to go through the plots and the code. Perhaps you can help me by narrowing down your question a bit. What is it that you expect from the PWM outputs and what is it you are getting instead?

  • 0 in reply to Gus Martinez
    Intellectual 755 points

    Hi Gus,

    In general, I wanted to confirm my inner PCMC loop at my board. I provided a constant RAMPMAXVALUE and set the output electronic load as CR. I tried to monitor whether my internal PCMC turns off at same peak current level for both positive and negative cycle in one PWM cycle. I get different peak levels when clamping diodes are mounted.

    Clamp diodes are mounted case is as below.

    I also get again different and mismatched peak current levels in other test, when I removed clamping diodes. It is close but not equal again.

    I'm trying to resolve why my PCMC system doesn't turn off switches at same level for each positive and negative cycle in a PWM cycle.

    Thanks in advance.

  • 0 in reply to Gokhan G.
    TI__Mastermind 29521 points

    I can't comment on why the peak current levels are mismatching. Are you observing an issue with the PWM outputs, or the behavior of the comparator subsystem? 

  • 0 in reply to Gus Martinez
    Intellectual 755 points

    Hi Gus,

    Comparator subsystem output generates events and drives PWM's. The issue seems related to CMPSS and its PWM configuration.

    PWM configuration that generates SYNCPER signal for CMPSS is as below.

    {
    unsigned long PeriodValue;

    PeriodValue = DEVICE_SYSCLK_FREQ / (2*GATE_FREQ);

    EALLOW;
    // MISC. Period Load Mode
    EPWM_setPeriodLoadMode(EPWM8_BASE, EPWM_PERIOD_SHADOW_LOAD);
    // Time-Base Submodule Configurations
    EPWM_setClockPrescaler(EPWM8_BASE,EPWM_CLOCK_DIVIDER_1,EPWM_HSCLOCK_DIVIDER_1);
    EPWM_setTimeBasePeriod(EPWM8_BASE, PeriodValue -1);
    EPWM_setTimeBaseCounter(EPWM8_BASE, 0);
    EPWM_setTimeBaseCounterMode(EPWM8_BASE, EPWM_COUNTER_MODE_UP);

    //
    // Phase Configuration and Set
    // Configure PWM base3 as slave
    // SetPhaseShift = Value*TBCLK = Value*10nsec
    EPWM_enablePhaseShiftLoad(EPWM8_BASE);
    EPWM_setPhaseShift(EPWM8_BASE, 2); // Will be clarified later on!
    EPWM_setSyncOutPulseMode(EPWM8_BASE, EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN);
    EPWM_setCountModeAfterSync(EPWM8_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);

    //
    // Counter-Compare Submodule Configurations
    EPWM_setCounterCompareShadowLoadMode(EPWM8_BASE,EPWM_COUNTER_COMPARE_A,EPWM_COMP_LOAD_ON_CNTR_ZERO);
    EPWM_setCounterCompareShadowLoadMode(EPWM8_BASE,EPWM_COUNTER_COMPARE_B,EPWM_COMP_LOAD_ON_CNTR_ZERO);


    EPWM_setCounterCompareValue(EPWM8_BASE, EPWM_COUNTER_COMPARE_A, 0);
    EPWM_setCounterCompareValue(EPWM8_BASE, EPWM_COUNTER_COMPARE_B, 0);

    HRPWM_setSyncPulseSource(EPWM8_BASE,HRPWM_PWMSYNC_SOURCE_ZERO);
    EDIS;
}

    Thanks in advance.

  • 0 in reply to Gokhan G.
    TI__Mastermind 29521 points
    Gokhan G. said:
    Comparator subsystem output generates events and drives PWM's. The issue seems related to CMPSS and its PWM configuration.

    It would help me immensely if you could narrow down your question to a specific feature or problem with the MCU as you have done on other forum posts. 

  • 0 in reply to Gus Martinez
    Intellectual 755 points

    Hi Gus,

    Actually I'm lack of ideas how to move forward on this issue. Maybe you and hardware developer can inspect waveforms together or you can guide me if you have any ideas.

    Thank you in advance.

  • 0 in reply to Gokhan G.
    TI__Mastermind 29521 points

    I noticed you configured the SYNCPER PWM differently than the PMP23126 design. In this design, the CMPC was used to control the location of the SYNCPER output signal. Have you tried just using this configuration?

    void PSFB_HAL_setupAdcOvrSamplPWM(uint32_t base1, uint16_t pwm_period_ticks)
{
    EALLOW;
    EPWM_setPeriodLoadMode(base1, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(base1, pwm_period_ticks - 1);
    EPWM_setTimeBaseCounter(base1, 2);
    EPWM_setPhaseShift(base1, 2);
    EPWM_setTimeBaseCounterMode(base1, EPWM_COUNTER_MODE_UP);
    EPWM_setClockPrescaler(base1, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    EPWM_enablePhaseShiftLoad(base1);

    HRPWM_setSyncPulseSource(base1, HRPWM_PWMSYNC_SOURCE_COMPC_UP);
    EPWM_setCounterCompareValue(base1, EPWM_COUNTER_COMPARE_C,
                                 pwm_period_ticks - 5);

    EDIS;
}

    In your code it looks like you simply want to pass the input SYNC signal to the output. So really, in this case I am not sure what is the point of configuring a separate PWM, i.e. you could just take the SYNC output signal from which ever PWM is feeding this signal as the CMPSS source. 

    Have you tried observing the CTRIPOUTH output using XBAR to debug this further?