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TMS320F280025: About analog subsystem ADCDACLOOPBACK register

Ben Qin
Intellectual 2690 points
Part Number: TMS320F280025


Hi Team,

There're some issues from the customer need your help:

1. I don't see any diagram about DAC to ADC loopback in TRM and DS, so i wonder how it loopback?

2. There are four comparators in analog subsystem, each comparator have high and low two DACs. So there are eight DACs in total. In following picture COMPDACA refer to which DAC? And connect to which ADCA and ADCC channels?

Could you help check this case?

Thanks & Regards,

Ben

  • +1
    TI__Genius 11081 points

    Hello Ben,

    When the loopback bit is set, the ADC will sample the output of CMPSS1 DACL (low DAC). As long as the bit is set, the configured ADC will sample the DACL output regardless of what channel is selected (the loopback setting overrides CHSEL). There is a special acquisition window requirement when sampling the internal COMPDAC output - at least 4.3us (430 cycles at 100MHz SYSCLK). The DAC output effectively has a 7-bit resolution in this case, even though the input to DACLVALA is a 12-bit value (IOW, discard the last 5 LSBs).

    This feature is intended for use as a diagnostic/self-test mechanism to confirm that ADCs are converting properly.

    I will follow up on an action to clarify the user manual on the use of this feature.

    Best regards,
    Ibukun