[28384D's MSGRAM address assignment.]
Since this post is written using a translator, the content may be unnatural.
hello.
I am writing because I have an inquiry while using 28384D.
I want to share data using only MSGRAM (between CPU1 and CM) without using IPC.
Each data consists of structures with different sizes.
The same structure is defined in each core of CPU1 and CM, and only the RAM location of '#pragma Data_section()' is different, everything is the same.
However, in the memory map, the address of each structure in the shared RAM is different.
Main question Q1) Is there any way to make the data order of CPU1 and CM the same in the memory map?
Can't the user define the order defined in the memory map?
(I'd like a better way than how to split a region of MSGRAM in a link file.)
Q2) Changed COFF -> EABI to use #pragma LOCATION(x, addr).
Is there anything else to be aware of other than the size change of DOUBLE?
Q3) I want to put the structure of gMENU_PQ at address 0x038400 using #pragma LOCATION(gMENU_PQ, 0x038400), but after debugging, gMENU_PQ disappeared.
Am I using it wrong? Or is it an unavailable command?
Q4) I know that you can declare the address of a variable in a link file.
After setting 'extern' in 'header file', I try to insert 'gMENU_PQ :> 0x038000' in link file, but it is the same symptom as when #pragma LOCATION(gMENU_PQ, 0x038400) is used. (Q3)
Is this method not available in TI Compiler?