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TMS320F28384S: CM interrupt nesting example

Carlo Taboni33
Intellectual 390 points
Part Number: TMS320F28384S

Hello,

I am developing an application on CM core with two interrupt sources: SYSTICK timer and UART. 

The SYSTICK IRQ is used to generate the system tick, and the UART IRQ is used to handle EOT events.

I need that the UART IRQ is serviced immediately, nesting eventually the SYSTICK handler execution.

Which is the best pattern to do this? I there a simple example?

On C28 core, I would have re-enabled interrupts, inside the tick handler routine, but on ARM core I guess there is a better way to do this, using the NVIC 'group of priorities' properties.

Thank you,

Carlo.

  • 0
    Expert 1776 points

    Hi Carlo,
    you are right about the simpler method on CM.
    You just need to set the priorities with the Interrupt_setPriority() function.
    If an interrupt has higher priority (lower number in the Interrupt_setPriority argument), than the NVIC takes care of the rest, and this interrupt will preempt every other interrupt with lower priority.

    Regards,
    Andy


  • 0 in reply to AndyP
    Intellectual 390 points

    Thank you Andy.

    I have assigned priority 0 to UART IRQ and 1 to SYSTICK IRQ.

    Just another question about the rule of priority grouping.

    The Interrupt_getPriorityGrouping() returns 0. Is it ok? If not, which value should I set? I am new to ARM cores and this concept is not clear for me.

    Thank you.

  • +1 in reply to Carlo Taboni33
    Expert 1776 points

    I have never used the PriorityGrouping functions because I never had the need. The value 0 returned when Interrupt_getPriorityGrouping() is read seems to be ok, and this value means that all the 8 priorities (0...7) are in the priority Group, not Subgroup.

    Look at the table from TRM:

    The implementation of NVIC in CM is such that from the all 256 priorities available (8 bits) in ARM, only 8 are used (3 bits). And the important thing is that these are 3 MSB bits. Look at the NVIC_IPRx registers - in each interrupt priority register part the lower 5 bits are not used.
    That means that in the PRIGROUP field, when you set values 0-4 it has the same effect - still all 8 priorities are in the same priority Group.

    Things will go different when higher values are set, eg. 0b101. In that case two bits are in Group priority, and one bit in Subpriority.
    In this example when you have three interrupts:
    INT1 - priority 0 (group/preempt priority 0, subgroup priority 0)
    INT2 - priority 1 (group/preempt priority 0, subgroup priority 1)
    INT3 - priority 2 (group/preempt priority 1, subgroup priority 0)
    then INT1 & INT2 are both in one preempt group 0. It means that both INT1 and INT2 can preempt INT3. But INT1 and INT2 cannot preempt each other (because they have the same preempt group). When INT2 and INT1 are both pending, INT1 will execute first and then INT2 after finishing INT1.

    I hope that all information I gave is correct.

    Regards,
    Andy

  • 0 in reply to AndyP
    Intellectual 390 points

    Thank you Andy for the fast and clear response.