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TMS320F28384D: The questions of SCI module.

Part Number: TMS320F28384D


Hi champs,

In below picture, we show the SCI communication format. My customer has two questions,

  1. What's the delay time before SCI starts sampling?
  2. Does SCI module samples signal at SCKCLK rising edge?

Please advise your comments, thanks for help.

Thanks and regards,

Luke

  • Luke,

    Thanks for your questions.

    What's the delay time before SCI starts sampling?

    The SCI should start sampling on the first full SCICLK period within the start bit, but won't count it as a valid start bit until four consecutive internal SCICLK periods of zero bits is detected. See this section from TRM:

    NOTE: if an SCI ISR is still being processed, it can prevent the sampling until ISR is completed. This is only within SCI interrupt, other interrupts will not stop it.

    Does SCI module samples signal at SCKCLK rising edge?

    I believe it completes one full SCICLK period starting with the rising edge. But it won't count as a "full" sample until it has completed 1 SCICLK period.

    I will verify whether this is correct with design experts:

    Could you provide context from customer for why this is being asked?

    Regards,

    Vince

  • Hi Vince,

    My customer is facing the UART host baud rate error problem, so he wants to know how to determine the tolerable maximum baud rate error.

    Regards,

    Luke

  • Hi Luke,

    Thanks, I am still waiting on further reply from design experts on whether it is rising or falling edge.

    Regards,

    Vince

  • Hi Luke,

    Confirmed with design, this is indeed a rising edge to detect first period. The 7th sample period is when the device chooses whether the bit is a valid value (after majority vote on 4th, 5th, and 6th sample period).

    Regards,

    Vince