Hi team,
1) Using TMS320F28377D, EMIF1 bus with SDRAM, FPGA, and dual port RAM mounted, CPU1 requires access to SDRAM and FPGA, and CPU2 requires access to dual-port RAM. Can the EMIF1 bus switch back and forth between CPU1 and CPU2?
2) If so, is there any delay in this switching bus? Will access to external devices be affected?
Thanks.
Best,
Cherry