Part Number: TMS320F28386D
Other Parts Discussed in Thread: C2000WARE
I am using SPI to TX Data with FIFO(SPI_FIFO_TX16), but using polling method not use interrupt(Project limited interrupt usage).
For example, When Tx the data(The tx bytes which shall less than 16 determined by in the short time, the data move to HWREGH(base + SPI_O_TXBUF))
I had done the test, If I put DELAY_US(4); Then it will TX as the first picture shows. Two SPI communication cycles.
If I put DELAY_US(3); Then it will TX as the second picture shows. One SPI communication cycles.
My questions is where I can find the parameter description of timeout of TX with fifo? To TX as one or two SPI communication cycles
I suppose this may in datasheet.
void spiTxFIFOTask(const uint8_t dataTx[],const uint8_t byteLength)
{
// Require that dataTx and dataRx are not NULL pointers
assert(dataTx);
uint16_t i;
//
// Send data
//
for(i = 0; i < byteLength; i++)
{
SPI_writeDataNonBlocking(SPID_BASE, dataTx[i]<<8);
}
}
