Part Number: TMS320F280039
Hi,
Some doubts about PWM operation in AC/DC topology, 100KHz PWM frequency, 10KHz control frequency, up mode, 16ch PWM used, with phase shift, fixed 50% duty, CLA is used to calculate the phase value and update it at CTR=zero, with shadow register.
1) If the phase value is less than CMPA/B (50% duty), everything is OK.
2) If the phase value is larger than CMPA/B, after new phase updated, CTR is larger than CMPA/B, in one PWM cycle, the compare between CMPA and CTR is missed, and the new PWM wave is not updated. It's not acceptable in customer's application.
What can we do?
CLB is not enough handle 14ch PWM. So SW CLA ISR was used to force PWM low or high in case 2. In this case, 14ch PWM's AQSFRC was used. we found that, 7 codes like EPwm8Regs.AQSFRC.bit.OTSFA=1 cost about 1us. In another way, AQSFRC's address was used, 7 codes *address = *address + 4 cost about 600ns. Is there any other way, to decrease the cost to less than 150ns, for example assembly code?
Thanks a lot.
Br, Jordan
