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TMS320F28379D: CLB working frequency

Part Number: TMS320F28379D


From E2E design support forums, I get the information that the highest frequency of CLB is 100 MHz and it is clocked to the EPWM with a divider.

From:e2e.ti.com/.../launchxl-f28379d-launchxl-f28379d-clb-clock-frequency

Based on this information I have following questions

1. The EPWM highest working frequency is 200MHz. EPWM module has lot of outputs to CLB. This outputs are signal with highest frequency of 200MHz. So how can I config the CLB to guarantee the CLB module(100MHz) can process the input signal from EPWM? Or if the signal timing width is smaller than CLB timing period, CLB cannot deal with this situation?

2. Also from Table26-2 I find CLB has local input from  ECAP/CPU outputs which working frequency may be 200MHz? How can I config the CLB for these input signal?

  • Hello,

    The EPWM highest working frequency is 200MHz

    Can you tell me where you found this info? I checked the datasheet and some of our other resources, and all I could find was that the ePWM's maximum frequency for the F2837xD device is 100 MHz.

    So how can I config the CLB to guarantee the CLB module(100MHz) can process the input signal from EPWM? Or if the signal timing width is smaller than CLB timing period, CLB cannot deal with this situation?

    Generally if you're trying to route in a specific signal, I recommend following the CLB Input Selection section of the CLB chapter in the technical reference manual. This section describes what filters/synchronization configurations are needed for different signals that are being used as CLB inputs. Generally, if the signal is changing faster than the CLB Tile clock, these changes will be missed (but this would essentially be passing in a 200 MHz clock signal into the CLB), there is no configuration I know of within the CLB to account for this.

    Also from Table26-2 I find CLB has local input from  ECAP/CPU outputs which working frequency may be 200MHz? How can I config the CLB for these input signal?

    What I said before applies here too; if you're passing something like a 200 MHz clock signal into the CLB Tile the Tile will not be able to see every change that's happening at 200 MHz. However, keep in mind that signals from the eCAP or other peripherals don't necessarily toggle at this rate, so it may or may not affect the CLB Tile logic depending on what sort of signal you're passing through (essentially any pulse that is less than 10 ns). You can think of this as undersampling a signal, if that makes sense.

    The reason for the lowered max CLB Tile frequency as compared to other peripherals comes from the fact that the CLB Tile logic goes through many paths for inputs/logic.

    Best regards,

    Omer Amir

  • https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1110125/launchxl-f28379d-launchxl-f28379d-clb-clock-frequency?tisearch=e2e-sitesearch&keymatch=CLB%2520CLOCK#

    From this article, the third anwser said the CLB is clocked to the EPWM with a divider in 28379D.  Can you provide more information about this divider?How to config this divider? Can CLB and EPWM working at same frequency?

  • Hello,

    You can control the ePWM clock divider with the EPWMCLKDIV bit in the PERCLKDIVSEL register, the details on clocking are in the Clocking section of the System Control chapter of the technical reference manual.

    Can CLB and EPWM working at same frequency?

    Let me verify this, I want to check how the CLB tile/register clock is configured for this device.

    Best regards,

    Omer Amir

  • Hello,

    I've confirmed that the CLB is clocked by the same clock as the ePWM for the Tile clock, and the register clock comes from the system clock. It should follow the image below:

    Best regards,

    Omer Amir