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TMS320F28377D: CPU and CLA data sharing - using LSRAM vs dedicated CpuToCla1MsgRAM / Cla1ToCpuMsgRAM

Tal Sorek
Prodigy 20 points
Part Number: TMS320F28377D

Hello,

These questions might have been asked before, but I have not been able to find conclusive answers. 

In my program I have already implemented usage of the CLA core and been running control routines in real time using it. In parallel, the CPU is running and there is data that is constantly been shared between the CPU and CLA.

My main concern is that for some reason false/garbage data will be read by either the CPU or CLA in one of the LSRAM blocks, either when one of the masters is trying to read the data simultaneously when the other one is writing to it or for some other reason.

In the data sheet section 3.11.1.6 Access Arbitration -> Figure 3-15. Arbitration Scheme on Local Shared Memories shows the arbitration scheme when trying to access the same memory from both the CPU and CLA. I am also aware that LSRAM blocks can be configured to have CPU write protection (by setting the CPUWRPROT_LSx bit to 1).

Additionally, section 6.3.1 CLA Memory also talks about "CPU to CLA Message RAM" and "CLA to CPU Message RAM"

"The CLA can use this block to pass data to the CPU. This block is both readable and writable by the CLA. This block is also readable by the CPU but writes by the CPU are ignored."

So following this long intro (sorry Slight smile), here are my main questions :

  1. What would be considered a more "safe" method regarding CPU write protection? is it using Cla1ToCpuMsgRAM to pass data from the CLA (memory is small and can be insufficient) or using LSRAM block and activating the CPU write protection?
  2. In the opposite direction, assuming my CLA code will never try to 'write' to the data sent from the CPU, is it more "safe" to have it shared using the CpuToCla1MsgRAM or using one of the LSRAM blocks when configured both CLA and CPU to be masters?
  3. When trying to 'read' data from an LSRAM block, I understand that it follows the arbitration as stated in Section 3.11.1.6, is reading from CpuToCla1MsgRAM follows a similar arbitration? I want to make sure that writing to the data is completed before someone is trying to read from it.

Thanks in advance.

  • +1
    TI__Guru* 91990 points
    Tal Sorek said:
    What would be considered a more "safe" method regarding CPU write protection? is it using Cla1ToCpuMsgRAM to pass data from the CLA (memory is small and can be insufficient) or using LSRAM block and activating the CPU write protection?

    Either option is effective in blocking the CPU from writing to the memory.

    Tal Sorek said:
    In the opposite direction, assuming my CLA code will never try to 'write' to the data sent from the CPU, is it more "safe" to have it shared using the CpuToCla1MsgRAM or using one of the LSRAM blocks when configured both CLA and CPU to be masters?

    If by safe you mean protect from unintended writes by the CLA, then the message RAM will block writes from the CLA. 

    Tal Sorek said:
    When trying to 'read' data from an LSRAM block, I understand that it follows the arbitration as stated in Section 3.11.1.6, is reading from CpuToCla1MsgRAM follows a similar arbitration? I want to make sure that writing to the data is completed before someone is trying to read from it.

    Yes, the message RAM arbitration is described in the CLA chapter of the technical reference manual (TRM). In the current TRM it is section 6.4. Note if you will be updating a number of values and want the other CPU to wait then I suggest implementing some sort of handshake between the two. This could be an interrupt back to the C28x, or a flag, as an example.

  • 0 in reply to Lori Heustess
    Prodigy 20 points

    Hi Lori, Thanks for your answer.

    So just to be clear and ease my mind - I do not need the other CPU to wait for a few values to be updated, my main concern is having some false data being read by the CLA when it is being updated by the CPU.

    So, if I understand correctly there shouldn't be any problem using either LSRAM or the CpuToCla1MsgRAM  to share data between the two because both RAMs have their own memory access arbitration scheme, which will make sure this kind of situation can not happen, is that correct?

    Thanks again

    Tal.

  • +1 in reply to Tal Sorek
    TI__Guru* 91990 points

    Correct. All of the RAMs on this device are SARAM (single-access RAMs) plus there is an arbitration scheme that determines which access goes first. 

  • 0 in reply to Lori Heustess
    Prodigy 20 points

    Hi,

    Thanks for answering all my questions. Have a great day.