LAUNCHXL-F280049C: Rom Boot to flash & reset button fails INTOS1

I'm having a little trouble following your description. Are you porting your application from F28004x to F28002x? Are you saying it successfully boots to main, but is failing to make it past the clock initialization depending on which INTOSC you choose?

Do note that the recommended clock initialization routines are different between F28004x and F28002x, so make sure that you are using the appropriate driverlib for your device.

As far as linker command files go, BEGIN is the key section for booting from flash. Flash entry point (0x80000) is the same between these two devices. Beyond that, F28002x only has bank 0, but it's at the same location. How you divide it up between code and data shouldn't matter much as long as code start goes at 0x80000. Are you using the default CodeStartBranch.asm file from C2000Ware or have you customized it?

Whitney

Whitney Dewey said:

I'm having a little trouble following your description. Are you porting your application from F28004x to F28002x?

No, from 4x configured for 2x hal.c and yes below used to set INTOS2 derived via 4x, not 2x 

// Set up PLL control and clock dividers
// PLLSYSCLK = 20MHz (XTAL_OSC) * 10 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
CLK_Missing = SysCtl_setClock(SYSCTL_OSCSRC_XTAL |
SYSCTL_IMULT(5) |
SYSCTL_FMULT_NONE |
SYSCTL_SYSDIV(1) |
SYSCTL_PLL_ENABLE); 

Whitney Dewey said:

Are you saying it successfully boots to main, but is failing to make it past the clock initialization depending on which INTOSC you choose?

Correct, there is No XCLKOUT via GPIO J2-pin 15 when we push reset button after ending debug or UniFlash or POR. Only has XCLKOUT 25MHz from INTOS2 via UniFlash run or run from CCS debug INTOSC1? it seems. The same basic ROM Boot to flash works in the SDK firmware when loaded but not the MCSDK derived from pragma sections of F28002x_flash_is_cpu_eabi.cmd but with Flash sector addresses of x49c.

Whitney Dewey said:

Are you using the default CodeStartBranch.asm file from C2000Ware or have you customized it?

It's the one from SDK4.0 x49c project ported to MCSDK.  

SECTIONS
{
codestart : > BEGIN, PAGE = 1, ALIGN(4)

Notice a major difference how flash sectors 2x were configured versus 4x CMD file. Commented BOOT/CODE lines made no difference. Appears code was never tested to boot from flash other than perhaps CCS debug. I recently reported a similar issue where SDK4.0 pragma section was corrupted during POR ROM boot to flash. Yet INTOS2 was producing XCLOCKOUT after reset button pushed and UniFlash too but not after POR cause NMI fault. I have not had any NMI faults in debug runtime of the universal motor control, MCSDK.

MEMORY
{
PAGE 0 :

/* Flash sectors */
/* BANK 0 */
// FLASH_BANK0_SEC0 : origin = 0x080002, length = 0x000FFE /* on-chip Flash */
FLASHBANK0_BOOT : origin = 0x080002, length = 0x000FFE /* remote update */
FLASHBANK0_CODE : origin = 0x081000, length = 0x00D000 /* control code */

/* BANK 1 */
// FLASH_BANK1_SEC0 : origin = 0x090000, length = 0x001000 /* on-chip Flash */
// FLASH_BANK1_SEC1 : origin = 0x091000, length = 0x001000 /* on-chip Flash */

PAGE 1 :

   BOOT_RSVD        : origin = 0x000002, length = 0x0000F3      /* Part of M0, BOOT rom will use this for stack */

/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RESET : origin = 0x3FFFC0, length = 0x000002

Whitney Dewey said:

Are you using the default CodeStartBranch.asm file from C2000Ware

This code branch was part of SDK 4.0 project copied to MCSDK project and of course excluded any x2 files from the build. 

***********************************************************************

WD_DISABLE  .set  0    ;set to 1 to disable WD, else set to 0

    .ref _c_int00
    .global code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB _c_int00         ;Branch to start of boot._asm in RTS library
    .endif

;end codestart section

***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
    .if WD_DISABLE == 1

    .text
wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    LB _c_int00         ;Branch to start of boot._asm in RTS library

    .endif

;end wd_disable

    .end

;//
;// End of file.
;//

Whitney Dewey said:

Where are the internal oscillators being used? Only to run XCLKOUT but not SYSCLK?

XCLOCK out only works with INTOSC2 in UniFlash and assuming CCS debug. As XCLOCKOUT is missing when POR or reset button is pushed upon exiting, ending XDC110 debug state. 

Whitney Dewey said:

WD_DISABLE in the CodeStartBranch.asm file to 1.

It is disabled in hal.c so CodeStartBranch should leave it disable. The WD peripheral timeout is not even configured so why is CSB trying to enable it is the bigger question? Seemingly the WD is executing before the CPU even loads the IP due to CSB doing unexpected things with a disabled peripheral.

Whitney Dewey said:

One thing we recommend when people are having trouble getting booting from flash to work

It was disabled in 2x CSB but not in 4x of the original SDK4.0 and that was having POR Boot to flash issues for reasons other than WD being enabled. Hence totally bamboozled, bewildered and few other B words come to mind 

Thank you Whitney, that explains a lot of the mystery though haven't done anything with C2000 WD up to this point.