Other Parts Discussed in Thread: TMS320F28335
Hi everybody,
I'm using a TMS320F28335 DSP and a TMS320C2000 C/C++ Codegen PC v5.2.1.
Trying to fix a problem in an assembly routine (two different possible solutions), some doubts are now arising on why the second solution doesn't work.
Problem: inside the assembly routine after a PUSH ST0 (16-bit register) there is a PUSH XT (32-bit register). The latter overwrote ST0 on the stack because every 32-bit operation requires the stack to be evenly aligned; if not so, the processor would impose an even alignment storing the register at (SP-1), thus overwriting what was already there.
My first (and working) solution: add a PUSH ST1 after the PUSH ST0 to align the stack.
Second possible solution:
ASP
PUSH XT
...
POP XT
NASP
Unfortunately this doesn't work! The program goes completely crazy causing an "Illegal-instruction TRAP" (in my opinion very likely due to a misaligned stack).
I've been told by someone in TI it should work but I'm convinced it is dangerous (risky).
My explanation below.
When the compiler generates assembly code for a C-written interrupt routine, it adds an ASP instruction firstly. This is well documented in the manual.
I imagine (please confirm) that in doing so the compiler relies on an even-aligned stack in the following generated assembly code.
Now, let’s suppose that an
assembly routine (hand-written), called from within this interrupt
routine, uses in its turn ASP / NASP instructions: here I may see some
problems.
_interruptFunction:
ASP
-----------------------------> Here the stack is even-aligned
…
LCR #_handWrittenAssemblyFunction
----------------------------------------------------> Returning from the function, SP = 0x4, SPA = 0. The stack is still EVEN-aligned but SPA changed to 0
…
…
…
NASP
_handWrittenAssemblyFunction:
----------------------------------------------------> Suppose that here SP = 0x4, SPA = 1 (in ST1 register)
PUSH ST0
----------------------------------------------------> SP = 0x5, SPA = 1
...
ASP
----------------------------------------------------> SP = 0x6, SPA = 1
PUSH XT
...
POP XT
----------------------------------------------------> SP = 0x6, SPA = 1
NASP
----------------------------------------------------> SP = 0x5, SPA = 0
...
POP ST0
----------------------------------------------------> SP = 0x4, SPA = 0
LRETR
Any ideas / suggestions?