Other Parts Discussed in Thread: DRV832X
Hello,
Why does build level 2 start & run motor 3.5A and easily force OVC trip fault 2.5A via CMPSS DACH/L. Then build level 3 OVC fault trip 6.5A during startup spins motor then cause OVC fault via CCMPS DAC-L/H, mostly H latch? Note both levels required ADC_FULL_SCALE_CURRENT setup as P2P ±2048 being 1.3A rated motor required to set OVC fault trip point 6.5A in open loop build level 2. Oddly stall current (2.9f) and the rotor spins then stalls as it passes 2.9A and OVC occurs in closed loop DMC level 3. ADC full scale current (4096 counts) via CMPSS DACH/L values were based on P2P current ±2048 based on the PWM action qualifiers for DACA1-H/L DACB1-H/L being H or L. My C code case DAC latches remain high impedance state until comparator +Input level exceeds the preset values below. However, the invert state of DACB1-L output does not remain high impedance, for unknown reason that condition could not be qualified in both MCSDK or SDK hal.c..
obj->dacCMPValH = 2048 + cmpValue;
obj->dacCMPValL = 2048 - cmpValue;
Notice: objSets->maxPeakCurrent_A = (USER_M1_ADC_FULL_SCALE_CURRENT_A * 0.495f); Perhaps ADC full scale current might check P2P as it seems more accurate measure via CMPSS DACSH/L.
Could USER_M1_FAULT_CHECK_CURRENT_A (0.05f) be to low being well below stall trip fault level? Can to low setting be reason why OVC occur during closed loop motor run but not during open loop?
Oddly current trip testing build level 2 defaults to USER_M1_MAX_VS_MAG_PU (0.576) without any current reconstruction being noticed in the code. So I reduced ~MAG_PU to 0.5 and it still OVC faults during closed loop startup and we have to manually clear moduleOverCurrent bit after clearing flag is forced set 1. Something in the clear fault bits code does not allow all bits to be cleared by motorVars_M1.flagClearFaults being set 1. However faults clearing worked great in SDK4.0 when we set motorVars_M1.faultMtrUse.all to 0 it cleared all fault flag bits.
In conclusion the motor attempts to run closed loop but trips OVC in the above examples of build level 3 and not in build level2. Seems illogical that we can cause a forced OVC trip at much lower (2.5A) build
level 2 and can't get motor running from the same ADC inputs at twice the OVC trip level (6.5A) in build level 3. What should we be looking at that is causing this mayhem?
DMC build level 2: I set the USER_M1_FAULT_CHECK_CURRENT_A threshold 1.35A but requires set motorSetVars_M1.overCurrent_A (2.25A) to get motor running without driving OVC trip, mostly DACA1-H latches of 3 CMPSS also build level 3 similar results. The OVC trip point in open loop is <0.8A so why does it trip OVC in build level 3 when starting up?
#define USER_MOTOR1_FORCE_DELTA_A (0.05f) // A
#define USER_MOTOR1_ALIGN_DELTA_A (0.01f) // A
#define USER_MOTOR1_FLUX_CURRENT_A (0.325f) // A
#define USER_MOTOR1_ALIGN_CURRENT_A (0.325f) // A
#define USER_MOTOR1_STARTUP_CURRENT_A (0.325f) // A
#define USER_MOTOR1_TORQUE_CURRENT_A (0.65f) // A
#define USER_MOTOR1_OVER_CURRENT_A (2.25f) // A
